Home Faculty SOC Group Hongchin Lin Professor

Hongchin LinProfessor - SOC Group
Tel
886-4-22851549-250
E-Mail
hclin@nchu.edu.tw
Lab
High-Speed Integrated Circuits Lab 610
Education
Ph.D. Electrical Eng., U. of Maryland, College Park
Experiences
Professor, Department of Electrical Engineering, National Chung Hsing University, 02/2003-present
Associate Professor, Department of Electrical Engineering, National Chung Hsing University, 02/1995-01/2003
Senior Engineer, Advanced Micro Devices, Sunnyvale, California, U.S.A., 09/1992-02/1995
Research Assistant, Department of Electrical Engineering, University of Maryland, U.S.A., 08/1989-08/1992
Teaching Assistant, Department of Electrical Engineering, University of Maryland, U.S.A., 01/1988-05/1989
Research Areas
Low-Power and High-Speed IC Design, Communication IC Design, Non-volatile Memory Circuit Design
Academic Service
Awards
Selected Publications
● Journal Paper 
1.
Yun-Ching Tang, Hong-Ren Wang, Hongchin Lin, and Jun-Zhe Huang, “Design of An Area-Efficient High-Throughput Shift-Based LDPC Decoder,” Journal of Circuits, Systems and Computers, vol. 6, no. 22, 08 2013. (EI、SCI)
2.
Boy-Yiing Jaw and Hongchin Lin, “Reduced-Ripple P-channel Metal-Oxide-Semiconductor Field-Effect Transistor Charge Pump Circuit with Small Filtering Capacitance,” Japanese Journal of Applied Physics, no. 51, pp. 02BE09-1~02BE09-5, 02 2012. (EI、SCI)
3.
ChihYang Huang and Hongchin Lin, “High-Voltage Tolerant Level Converter Circuit for Embedded CMOS Non-volatile Memories,” Japanese Journal of Applied Physics, no. 51, pp. 02BE08-1~02BE08-4, 02 2012. (EI、SCI)
4.
Chao-Jui Liang, Chiu-Chiao Chung, and Hongchin Lin, “A Low-Voltage Band-gap Reference Circuit with Second-Order Analyses,” International J. Circuit Theory and Applications, no. 39, pp. 1247-1256, 12 2011. (EI、SCI)
5.
Chien-pin Hsu and Hongchin Lin, “Analytical Models of Output Voltages and Power Efficiencies for Multi-stage Charge Pumps,” IEEE Trans. Power Electronics, vol. 6, no. 25, pp. 1375-1385, 06 2010. (EI、SCI)
6.
Chien-pin Hsu and Hongchin Lin, “Enhanced P-channel Metal-Oxide-Semiconductor Field-Effect Transistor Charge Pump for Low Voltage Applications,” Japanese Journal of Applied Physics, no. 49, pp. 04DE16-1~04DE16-6, 04 2010. (EI、SCI)
7.
Chien-pin Hsu and Hongchin Lin, “A P-channel Metal-oxide-semiconductor Field-effect Transistor Charge Pump for Low Supply Voltages,” Japanese Journal of Applied Physics, no. 48, pp. 04C069-1- 04C069-5, 04 2009. (EI、SCI)
8.
Nansen Chen and Hongchin Lin, “Evaluation of Multi-Gbps Serial Link Using Wire-Bonded Multiple Exposed Pads (M-pad) Leadframe Package,” Microsystem Technologies, vol. 3, no. 15, pp. 367-374, 03 2009. (EI、SCI)
9.
Chiu-Chiao Chung, Hongchin Lin, and Yen-Tai Lin, “A Multilevel Read and Verifying Scheme for Bi-NAND Flash Memories,” IEEE J. Solid-State Circuits, vol. 5, no. 42, pp. 1180-1188, 05 2007. (EI、SCI)
10.
Po-Hsuan Huang, Hongchin Lin, and Yen-Tai Lin, “A Simple Subthreshold CMOS Voltage Reference Circuit with Channel Length Modulation Compensation,” IEEE Trans. Circuits and Systems II, vol. 9, no. 53, pp. 882-885, 09 2006. (EI、SCI)
11.
Nansen Chen, Hongchin Lin, and J. Y. Lai, “Cost-Effective Chip-On Heat Sink Leadframe Package for 800 Mb/s/Lead Applications,” IEEE Trans. Advanced Packaging, vol. 2, no. 29, pp. 364-371, 05 2006. (EI、SCI)
12.
Chiu-Chiao Chung, Hongchin Lin, and Yen-Tai Lin, “A Novel High-Speed Sense Amplifier for Bi-NOR Flash Memories,” IEEE J. Solid-State Circuits, vol. 2, no. 40, pp. 515-522, 02 2005. (EI、SCI)
13.
T.-S. Chao, W.-M. Ku, Hongchin Lin, D. Landheer, Y.-Y. Wang, and Y. Mori, “CoTiO3 High-k Dielectrics on HSG for DRAM Applications,” IEEE Trans. Electron Devices, vol. 12, no. 51, pp. 2200-2204, 12 2004. (EI、SCI)
14.
Hongchin Lin, Jemin Lin and Robert C. Chang, “Inversion Layer Induced Body Current in SOI MOSFETs with Body Contacts,” IEEE Electron Device Letters, vol. 2, no. 24, pp. 111-113, 02 2003. (EI、SCI)
15.
Hongchin Lin and Funian Liang, “A High-Speed Current-Mode Multilevel Identifying Circuit for Flash Memories,” IEICE Transactions on Electronics, vol. 2, no. E86-C, pp. 229-235, 02 2003. (EI、SCI)
16.
Hongchin Lin, Nai-Hsien Chen and JainHao Lu, “Design of Modified 4-Phase CMOS Charge Pumps for Low-Voltage Flash Memories,” Journal of Circuits, Systems and Computers, vol. 4, no. 11, pp. 393-403, 09 2002. (EI、SCI)
17.
Hongchin Lin, Jack Tai-Yuan Chen and Jyh-Haur Chang, “Investigation of Disturbance for the New Dual Floating Gate Multilevel Flash Cells,” Solid-State Electronics, vol. 8, no. 46, pp. 1145-1150, 08 2002. (EI、SCI)
18.
Hongchin Lin and Kai-Hsun Chang, “Substrate-Connected High Voltage Pumping Circuits for Low Supply Voltages,” IEE Electronics Letters, vol. 13, no. 38, pp. 625-626, 06 2002. (EI、SCI)
19.
Hongchin Lin, Chia-Hsiang Sha and Shyh-Chyi Wong, “A Delay Model for DRAM Bit Lines with Step and Ramp Word Line Signals,” Solid-State Electronics, vol. 1, no. 46, pp. 145-151, 01 2002. (EI、SCI)
20.
Hongchin Lin, Jack Tai-Yuan Chen and Shyh-Chyi Wong, “A New Dual Floating Gate Flash Cell for Multilevel Operation,” Japanese Journal of Applied Physics, vol. 4B, no. 40, Part 1, pp. 126-131, 04 2001. (EI、SCI)
21.
Hongchin Lin, Chia-Hsiang Sha and Shyh-Chyi Wong, “An Analytical Delay Model for Read Operation at Any Position on Dynamic Random Access Memory Bit Lines,” Japanese Journal of Applied Physics, vol. 4B, no. 38, Part 1, pp. 2188-2193, 04 1999. (EI、SCI)
22.
Hongchin Lin and Yuang-Ching Sheu, “Parallel Computation of Space-dependent Boltzmann Transport Equation for Gate Current in MOSFET’s,” Journal of Engineering, National Chung Hsing University, vol. 3, no. 10, pp. 57-72, 03 1999.
23.
Hongchin Lin, et al., “A Comparison of Numerical Solution of the Boltzmann Transport Equation for High-Energy Electron Transport in Silicon,” IEEE Trans. on Electron Devices, vol. 9, no. 41, pp. 1646-1654, 09 1994. (EI、SCI)
24.
Hongchin Lin, Neil Goldsman, and Isaak D. Mayergoyz, “Device Modeling by Deterministic Self-Consistent Solution of Poisson and Boltzmann Transport Equations,” Solid-State Electronics, vol. 6, no. 35, pp. 769-778, 06 1992. (EI、SCI)
25.
Hongchin Lin, Neil Goldsman, and Isaak D. Mayergoyz, “An Efficient Deterministic Solution of the Space-Dependent Boltzmann Transport Equation for Silicon,” Solid-State Electronics, vol. 1, no. 35, pp. 33-42, 01 1992. (EI、SCI)
26.
Hongchin Lin and Neil Goldsman, “An Efficient Solution of the Boltzmann Transport Equation Which Includes the Pauli Exclusion Principle,” Solid-State Electronics, vol. 10, no. 34, pp. 1035-1048, 11 1991. (EI、SCI)
27.
Zeqi Pan, Hongchin Lin, and M. Dagenais, “Switching Power Dependence on Detuning and Current in Bistable Diode Laser Amplifiers,” Appl. Phys. Lett., no. 58, pp. 687-689, 1991. (EI、SCI)
28.
Hongchin Lin and Kawthar A. Zaki, “Properties of Three-Layer Dielectric Loaded Waveguides,” IEEE Trans. on Magnetics, no. 25, pp. 2950-2952, 1989. (EI、SCI)
● Conference Paper 
1.
Boy-Yiing Jaw and Hongchin Lin, “An Analysis of Output Ripples for PMOS Charge Pumps and Design Methodology,” IEEE Asia Pacific Conf. on Circuits and Systems, pp. 424-427, 12 2012. Kaohsiung, Taiwan,
2.
Kuo Ko and Hongchin Lin, “A Power-Efficient High-Voltage CMOS Gate Driver for Power MOS Transistors,” International Conference on Solid State Devices and Materials (SSDM), pp. 1146-1147, 09 2012. Kyoto, Japan,
3.
Boy-Yiing Jaw and Hongchin Lin, “An Analytical Model of Output Ripples for PMOS Charge Pump,” the 23rd VLSI Design/CAD Symposium, 08 2012. Kenting, Taiwan,
4.
ChihYang Huang and Hongchin Lin, “A High-Voltage Tolerant Interface Circuit for Embedded CMOS Non-volatile Memories,” International Conference on Solid State Devices and Materials (SSDM), pp. 170-171, 09 2011. Nagoya, Japan,
5.
Boy-Yiing Jaw and Hongchin Lin, “A Reduced-Ripple PMOS Charge Pump Circuit with Small Filtering Capacitors,” International Conference on Solid State Devices and Materials (SSDM), pp. 180-181, 09 2011. Nagoya, Japan,
6.
Chen-Hao Wu, Hongchin Lin and MingKai Wang, “A Multiple Time Programmable On-chip Trimming Technique for CMOS Bandgap Reference Circuits,” International Conference on Solid State Devices and Materials (SSDM), pp. 345-346, 09 2010. Tokyo, Japan,
7.
JianWei Chen, Hongchin Lin, Yun-Ching Tang, “Efficient High-Throughput Architectures for High-Speed Parallel Scramblers,” IEEE Int. Symp. Circuits and Systems, pp. 441-444, 05 2010. (EI)Paris, France,
8.
Chien-pin Hsu and Hongchin Lin, “An Enhanced PMOS Charge Pump for Low Supply Voltage Applications,” International Conference on Solid State Devices and Materials (SSDM), pp. 74-75, 10 2009. Sendai, Japan,
9.
Yun-Ching Tang, Do-Chen Hu, Weiyi Wei, Wen-Chung Lin, Hongchin Lin, “A Memory-Efficient Architecture for Low Latency Viterbi Decoders,” International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), pp. 335-338, 04 2009. (EI)Hsinchu, Taiwan,
10.
Nansen Chen and Hongchin Lin, “Investigation of Low Cost Consumer Electronic System Using 1066-Mb/s DDR2 Interface Design,” Intl. Conf. on Solid-State and Integrated-Circuit Technology (ICSICT), 10 2008. Beijing, China,
11.
Chien-pin Hsu and Hongchin Lin, “A PMOS Charge Pump for Low Supply Voltages,” International Conference on Solid State Devices and Materials (SSDM), pp. 1002-1003, 09 2008. Ibaraki, Japan,
12.
Nansen Chen and Hongchin Lin, “Design of Costless and Adjustable Inductors Embedded in Array Packages,” URSI Intl. Symp. on Signals, Systems and Electronics, pp. 383-386, 08 2007. Montreal, Quebec, Canada,
13.
Chien-pin Hsu and Hongchin Lin, “Analysis of Power Efficiency for Four-Phase Positive Charge Pumps,” IASTED Intl. Conf. on Circuits, Signals and Systems, pp. 15-19, 07 2007. (EI)Banff, Canada,
14.
Nansen Chen and Hongchin Lin, “Electrical Design and Manufacturing Evaluation for Multiple Exposed Pads (M-pad) Leadframe Package,” Intl. IEEE CPMT Symp. on High Density Design Packaging and Microsystem Integration, pp. 227-230, 06 2007. Shanghai, China,
15.
Chien-pin Hsu and Hongchin Lin, “Analysis of Power Efficiency for Four-Phase Negative Charge Pumps with Body Potential Control,” Intl. Conf. on IC Design and Technology, pp. 157-160, 05 2007. (EI)Austin, TX, U.S.A.,
16.
Hsin-Lei Lin, Hongchin Lin, R. C. Chang, S.-W. Chen, C.-Y. Liao, C.-H. Wu, “A High-Speed Highly Pipelined 2n-Point FFT Architecture for A Dual OFDM Processor,” Intl. Conf. Mixed Design of Integrated Circuits and Systems, pp. 627-631, 06 2006. Gdynia, Poland,
17.
Hongchin Lin and Dern-Koan Chang, “A Low-Voltage Process Corner Insensitive Subthreshold CMOS Voltage Reference Circuit,” Intl. Conf. on IC Design and Technology, pp. 227-230, 05 2006. (EI)Padova, Italy ,
18.
Nansen Chen, Hongchin Lin, Nan-Cheng Chen, Roger Wu, Tomson Chou, and Herbie Chien, “Integration Design of Chip and Package for Cost-Effective High-Speed Applications,” IEEE Conference on Electron Devices and Solid-State Circuits, pp. 621-624, 12 2005. Hong Kong, China,
19.
Hongchin Lin and Chao-Jui Liang, “A Sub-1V Bandgap Reference Circuit Using Subthreshold Curren,” IEEE Int. Symp. Circuits and Systems, pp. 2453-2456, 05 2005. (EI)Kobe, Japan,
20.
Chiu-Chiao Chung, Hongchin Lin, You-Min Shen and Yen-Tai Lin, “A Multilevel Sensing and Program verifying Scheme for Bi-NAND Flash Memories,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation, and Test (VLSI-TSA-DAT), 04 2005. (EI)Hsinchu, Taiwan,
21.
Hsin-Lei Lin, Hongchin Lin, Yu-Chuan Chen and Robert C. Chang, “A Novel Pipelined Fast Fourier Transform Architecture for Double Rate OFDM Systems,” Proc. IEEE Workshop on Signal Processing Systems, pp. 7-11, 10 2004. (EI)Austin, TX, U.S.A,
22.
Ming-chih Hsieh, Zheng-Hong Wang, Hongchin Lin and Yen-Tai Lin, “A New Dual Pumping Circuit without Body Effects for Low Supply Voltage,” IEEE Int. Symp. Circuits and Systems, vol. 2, pp. 621-624, 05 2004. (EI)Vancouver, Canada,
23.
Hongchin Lin, JainHao Lu and Yen-Tai Lin, “A Novel Charge Pump without Body Effects for 1.2V Flash Memories,” the 14th VLSI Design/CAD Symposium, pp. 365-368, 08 2003. Hualien, Taiwan,
24.
Funian Liang, Chiu-chiao Chung, Ming-chih Hsieh, Hongchin Lin, and Yen-Tai Lin, “A Robust High-Speed Low-Power Sense Amplifier for Flash Memories,” 14th VLSI Design/CAD Symposium, pp. 373-376, 08 2003. Hualien, Taiwan,
25.
Hsin-Lei Lin, R. C. Chang, Chih-Hao Huang, Hongchin Lin, “A Flexible Design of a Decision Feedback Equalizer and a Novel CCK Technique for Wireless LAN Systems,” IEEE Intl. Symp. on Circuits and Systems, vol. 2, pp. 153-156, 05 2003. (EI)Bangkok, Thailand,
26.
Hongchin Lin and Jemin Lin, “Parasitic Effects of Thin SOI MOSFETs with Body Contacts,” International Conference on Solid State Devices and Materials, pp. 600-601, 09 2002. Nagoya, Japan,
27.
Hongchin Lin, JainHao Lu and Yen-Tai Lin, “A New 4-Phase Charge Pump Without Body Effects for Low Supply Voltages,” Asia-Pacific Conference on ASICs, pp. 53-56, 08 2002. Taipei, Taiwan,
28.
Hongchin Lin, Wu-Chang Chang and Yen-Tai Lin, “An Area-Efficient CMOS Band-Gap Reference Circuit for Low Supply Voltage,” IEEE International Symposium on Circuits and Systems, vol. 3, pp. 663-666, 05 2002. (EI)Phoenix, Arizona, U.S.A,
29.
Dingtzay Chen and Hongchin Lin, “An 1V Rail-Rail Low-Power CMOS Op-Amp,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 309-312, 05 2002. (EI)Phoenix, Arizona, U.S.A,
30.
Hongchin Lin, Yi-Fan Chen and Hsien-Chih She, “A Low-Power 3-Phase Half Rail Pass-Gate Differential Logic,” IEEE International Symposium on Circuits and Systems, vol. 4, pp. 148-151, 05 2001. (EI)Sydney, Australia,
31.
Hongchin Lin and Nai-Hsien Chen, “New Four-Phase Generation Circuits for Low-Voltage Charge Pumps,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 504-507, 05 2001. (EI)Sydney, Australia,
32.
Hongchin Lin and Nai-Hsien Chen, “An Efficient Clock Scheme for Low-Voltage Four-Phase Charge Pumps,” Int. Symp. on VLSI Technology, Systems, and Applications, pp. 228-231, 04 2001. (EI)Hsinchu, Taiwan,
33.
Jack Tai-Yuan Chen, Hongchin Lin, Jyh-Haur Chang and Shyh-Chyi Wang, “Investigation of Disturbance for the New Dual Floating Gate Multilevel Flash Cells,” International Electron Devices and Materials Symposia, pp. 307-310, 12 2000. Chung-Li, Taiwan,
34.
Hongchin Lin, Chein-Zhi, and Funian Liang, “A Current-Mode level-Identifier for Read Operation in Multilevel Flash Memories,” the 11th VLSI Design/CAD Symposium, pp. 369-372, 08 2000. Taiwan, R.O.C,
35.
Hongchin Lin, Yun-Tso Lai, and Shyh-Chyi Wong, “Compact Expressions for Crosstalk of Multiple Bit Lines in DRAM,” International Conference on Solid State Devices and Materials, pp. 214-215, 08 2000. Sendai, Japan,
36.
Jack Tai-Yuan Chen, Hongchin Lin, and Shyh-Chyi Wong, “A New Dual Floating Gate Flash Cell for Multilevel Operation,” International Conference on Solid State Devices and Materials, pp. 282-283, 08 2000. Sendai, Japan,
37.
Hongchin Lin, Jie-Hau Huang, and Shyh-Chyi Wong, “A Simple High-Speed Low Current Comparator,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 713 -716, 05 2000. (EI)Geneva, Switzerland,
38.
Hongchin Lin, Chein-Zhi Chen, and Shyh-Chyi Wong, “A High-Speed Current-Mode Identifying Circuit for Multilevel Flash Memories,” Non-Volatile Semiconductor Memory Workshop, pp. 48-50, 02 2000. Monterey, California, U.S.A.,
39.
Ming-Feng Yu, Yung-Chang Lin, and Hongchin Lin, “Implementation of a Radix-4 Divider Using Domino Logic,” 10th VLSI Design/CAD Symposium, pp. 233-236, 08 1999. Nantou, Taiwan, R.O.C.,
40.
Hongchin Lin, Chein-Zhi Chen, and Shyh-Chyi Wong, “A Fast Parallel Current-Mode Multilevel Identifying Circuit,” the 10th VLSI Design/CAD Symposium, pp. 309-312, 08 1999. Nantou, Taiwan, R.O.C.,
41.
Hongchin Lin, Chia-Hsiang Sha and Shyh-Chyi Wong, “A Propagation Delay Model for Read Logic One in DRAM Bit Lines for DRAM Read Operation,” 1999 Semiconductor TCAD Workshop and Exhibition, 05 1999. Hsinchu, Taiwan, R.O.C.,
42.
Hongchin Lin, Kai-Hsun Chang, and Shyh-Chyi Wong, “Novel High Positive and Negative Pumping Circuits for Low Supply Voltage,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 238 -241, 05 1999. (EI)Orlando, Florida, U.S.A.,
43.
Hongchin Lin, Chia-Hsiang Sha and Shyh-Chyi Wong, “A Propagation Delay Model for Read Logic One in DRAM Bit Lines,” International Electron Devices and Materials Symposia, pp. 98-101, 12 1998. Tainan, Taiwan, R.O.C.,
44.
Hongchin Lin and Hsueh-yi Lin, “Simulations of IV Characteristics for Partially Depleted SOI MOSFET’s with Various Substrate Contacts,” International Conference on Next Decades of High Technologies, pp. 119-123, 11 1998. Taipei, Taiwan, R.O.C.,
45.
Hongchin Lin, Chia-Hsiang Sha and Shyh-Chyi Wong, “An Analytical Delay Model for Read Operation at Any Position on DRAM Bit Lines,” International Conference on Solid State Devices and Materials, pp. 38-39, 09 1998. Hiroshima, Japan,
46.
Hongchin Lin, Robert C. Chang and Sheng-Chou Tsai, “Radix-8 Divider Algorithm and Implementation,” the 9th VLSI Design/CAD Symposium, pp. 243-246, 08 1998. Nantou, Taiwan, R.O.C. ,
47.
Hongchin Lin and Yuang-Ching Sheu, “Parallel Computing of the Space-Dependent Boltzmann Transport Equation for Gate Current,” the 10th International Conference on Parallel CFD, pp. 15-3~15-6, 05 1998. Hsinchu, Taiwan, R.O.C.,
48.
Hongchin Lin, Yuang-Ching Sheu, Tien-Sheng Chao and Jian-Shihn Tsang, “Simulations of Gate Current in Deep Submicron Bulk and SOI N-MOSFET’s,” the 5th Symposium on Nano Device Technology, pp. 92-95, 05 1998. Hsinchu, Taiwan, R.O.C.,
49.
Hongchin Lin, “An Efficient Method to Investigate Degeneracy and Impact ionization Using Multi-band Structure of Silicon,” International Electron Devices and Materials Symposium, pp. 325-328, 12 1996. Hsinchu, Taiwan, R.O.C.,
50.
Hongchin Lin, Jack Z. Peng, Neil Goldsman, and Isaak D. Mayergoyz, “An Efficient Physics-Based Gate Current Calculation by Solving Space-Dependent Boltzmann Transport Equation,” Proceedings of the Eleventh Biennial University / Government / Industry Microelectronics Symposium, pp. 193-196, 05 1995. Austin, Texas, U.S.A.,
51.
林泓均, “An Application of Numerical Solution of Space-Dependent Boltzmann Transport Equation: Gate Current of MOSFET’s,” 1995 電腦應用研討會論文集, pp. 178-181, 04 1995.
52.
Hongchin Lin, Neil Goldsman, and Isaak D. Mayergoyz, “Deterministic BJT Modeling by Self-Consistent Solution to the Boltzmann, Poisson and Hole-Continuity Equations,” Proceedings of the International Workshop on Computational Electronics, pp. 55-59, 08 1993. Leeds, England,
53.
Hongchin Lin, Ken Hennacy, Neil Goldsman and Isaak D. Mayergoyz, “Efficient Self-Consistent Semiconductor Device Modeling by Deterministic Solution to the Boltzmann and Poisson Equations (Invited presentation),” IEEE MTT-S International Microwave Symposium, 06 1993. Atlanta, Georgia, U.S.A.,
54.
Hongchin Lin, Neil Goldsman, and Isaak D. Mayergoyz, “Deterministic Device Modeling of BJT’s by Improved Self-Consistent Solution to the Boltzmann and Poisson Equations,” Proceedings of the Ninth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits (NASECODE IX), pp. 7-8, 04 1993. Copper Mountain, Colorado, U.S.A.,
55.
Hongchin Lin, Neil Goldsman, and Isaak D. Mayergoyz, “An Efficient, Self-Consistent Method for Calculating the Distribution Function for an Entire Device,” Proceedings of the Eighth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits (NASECODE VIII), pp. 27-28, 05 1992. City Club, Vienna, Austria.,
56.
Hongchin Lin, Neil Goldsman, and Isaak D. Mayergoyz, “Improved Self-Consistent Device Modeling by Direct Solution to Boltzmann and Poisson Equations,” Proceedings of the International Workshop on Computational Electronics, pp. 143-146, 05 1992. Urbana-Champaign, Illinois, U.S.A.,
57.
Hongchin Lin, Neil Goldsman, and Isaak D. Mayergoyz, “Device Modeling by Deterministic Self-Consistent Solution of Poisson and Boltzmann Transport Equations,” Proceedings of International Semiconductor Device Research Symposium, pp. 435-438, 12 1991. Charlottesville, Virginia, U.S.A.,
58.
Hongchin Lin, Neil Goldsman, and Isaak D. Mayergoyz, “A Direct Solution to the Space-Dependent Boltzmann Transport Equation in Silicon,” Proceedings of Simulation of Semiconductor Devices and Processes (SISDEP), Vol. 4, pp. 195-204, 09 1991. Zurich, Switzerland,
● Book 
1.
王建智、林泓均, “SigmaRAM目標—高速網路之應用,” IC設計月刊, pp. 64-70, 03 2003.
2.
林泓均, “漫談快閃式記憶體之周邊電路設計,” IC設計月刊, pp. 55-59, 07 2001.
3.
Hongchin Lin and Yuang-Ching Sheu, “Parallel Computing of the Space-Dependent Boltzmann Transport Equation for Gate Current,” Parallel Computational Dynamics: Development and Application of Parallel Technology, C. A. Lin, A. Ecer, J. Peraux, N, Satofuka and P. Fox, eds., Elsevier Science, pp. 395-402, 01 1999.
● Technical Report 
1.
Hongchin Lin, “低功率多標準多媒體無線區域網路系統單晶片設計,” National Science Council, Final Report, 2004. (計畫編號: NSC92-2220-E-005-002) , 2004.
2.
Hongchin Lin, “子計畫三：多標準調變/解調變與時序回復等基頻處理器智產設計,” National Science Council, Final Report, 2004. (計畫編號: NSC92-2220-E-005-005), 2004.
3.
Hongchin Lin, “多階閘快閃記憶體之研究,” National Science Council, Final Report, 2003. (計畫編號: NSC 91-2215-E-005 -006), 2003.
4.
Hongchin Lin, “新型多階雙浮動閘快閃記憶體之研究,” National Science Council, Final Report, 2002. (計畫編號: NSC 90-2215-E-005 -001), 2002.
5.
Hongchin Lin, “高效率低電壓電荷抽灌電路,” National Science Council, Final Report, 2000. (計畫編號: NSC 89-2215-E-005 -001), 2000.
6.
Hongchin Lin, “平行處理多能帶波茲曼方程式之深次微米與毫微米元件模擬,” National Science Council, Final Report, 1999. (計畫編號: NSC 88-2213-E-005-011), 1999.
7.
Hongchin Lin, “毫微米MOS元件之高能量電子模擬,” National Science Council, Final Report, 1998. (計畫編號:NSC86-2215-E-005-002), 1998.
8.
Hongchin Lin, “深次微米SOI元件模擬與可靠度分析,” National Science Council, Final Report, 1998. (計畫編號:NSC87-2215-E-005-003), 1998.
9.
林泓均, “超大型積體電路設計實驗,” 教育部: 超大型積體電路科技教育改進計畫 (授課教師, 87/8/1~88/7/31) , 1998.
10.
Hongchin Lin, “Efficient Advanced Device Modeling for MOSFET’s Using Multi-band Boltzmann Transport Equations,” National Science Council, Final Report, 1997. (計畫編號:NSC85-2215-E-005-004), 1997.
11.
Hongchin Lin, “平行處理波茲曼傳輸方程式之半導體元件模擬,” National Center for High-performance Computing, Final Report, 1997. (計畫編號:NCHC-86-03-003), 1997.
12.
Hongchin Lin, “電子束微影成像於深次微米元件可行性評估-子計畫三: 深次0.1微米元件之電腦模擬與視覺化處理,” National Science Council, Final Report, 1997. (計畫編號:NSC85-2745-4-321-002), 1997.
13.
林泓均, “數位超大型積體電路設計,” 教育部: 超大型積體電路科技教育改進計畫(授課教師, 86/8/1~87/7/31) , 1997.
● Patent 
1.
Hong-Chin Lin, Jain-Hao Lu, Nai-Hsien Chen, and Chien-Hung Ho, “Charge pump circuit without body effects,” U.S. Patent 6888400, 05 2005.
2.
林泓均、謝明志、盧建豪、何建宏, “四相雙昇壓電路,” 中華民國發明專利，第I229499號，專利期間:94年3月11日~98年3月10日, 03 2005.
3.
Hong-Chin Lin, Jain-Hao Lu, Nai-Hsien Chen, and Chien-Hung Ho, “Charge pump circuit without body effects,” U.S. Patent 6642773, 11 2003.
4.
Hongchin Lin, Chien-Zhi Chen and Shyh-Chyi Wong, “Current-mode identifying circuit for multilevel flash memories,” U.S. Patent 6 459 613, 10 2002.
5.
Hong-Chin Lin, Fu-Nian Liang and Ching-Yuan Lin, “Current-mode sense amplifier with low power consumption,” U.S. Patent 6 4249 191, 09 2002.
6.
Hong-Chin Lin, Jie-Hau Huang and Shyh-Chyi Wong, “Current comparator,” U.S. Patent 6 424 183, 07 2002.
7.
Hongchin Lin, Kai-Hsun Chang and Shyh-Chyi Wong, “Charge-pumping circuits for a low-supply voltage,” U.S. Patent 6 359 501, 03 2002.
8.
Hongchin Lin and Shyh-Chyi Wong, “SOI structure with a body contact,” U.S. Patent 6 348 714, 02 2002.
9.
Hongchin Lin, Shyh-Chyi Wong, Chien-Zhi Chen and Chia-Hsiang Sha, “Method and circuit for measuring the read operation delay on DRAM bit lines,” U.S. Patent 6 088 273, 07 2000.
10.
Hongchin Lin, Kai-Hsun Chang and Shyh-Chyi Wong, “Charge pump circuits for low supply voltages,” U.S. Patent 6 037 622, 03 2000.
11.
林泓均、王是琦、陳泰元, “多階記憶單元,” 中華民國發明專利，第134343I號，專利期間:90年6月7日~109年1月10日.
12.
林泓均、張凱勛、王是琦, “低電壓充電泵浦電路,” 中華民國發明專利，第130295I號，專利期間:90年4月11日~108年6月6日.
13.
林泓均、王是琦、陳建志、施家祥, “DRAM位元線讀取延遲量測方法及結構,” 中華民國發明專利，第126413I號，專利期間:90年1月21日~108年1月21日.
14.
林泓均、張凱勛、王是琦, “應用於低供應電壓之充電泵電路,” 中華民國發明專利，第150393I號，專利期間:91年2月11日~109年2月10日.
15.
林泓均、王是琦, “具有基底接觸之絕緣層上有矽之結構,” 中華民國發明專利，第147466I號，專利期間:90年12月21日~109年4月18日.
16.
林泓均、黃志豪、王是琦, “高速低電流比較器,” 中華民國發明專利，第160815I號，專利期間:91年8月11日~109年12月10日.
17.
張呈源、黃志豪、林泓均、楊谷章、張永賢、趙軒慶, “互補碼解調變架構,” 美國/中華民國發明專利(pending).
18.
林泓均、陳迺賢、盧建豪、何建宏, “無體效應影響之電壓提昇電路,” 中華民國發明專利，第192239號，專利期間:92年12月1日~95年11月30日.
19.
林泓均、陳奕帆, “三相半軌通過閘差動邏輯電路,” 中華民國發明專利，公告第00534538號，專利期間:92年5月21日~102年6月14日.
20.
林泓均、梁甫年、林慶源, “低功\率消耗之快閃記憶體的感測電路,” 中華民國發明專利，公告第00546660號，專利期間:92年8月11日~111年1月18日.
21.
林泓均、王是琦、陳建志, “供多階快閃記憶體用之快速低電壓電流模式識別電路,” 中華民國發明專利，第170089I號，專利期間:92年1月11日~110年7月10日.
22.
林泓均、陳迺賢、盧建豪、何建宏, “無體效應影響之電壓提昇電路,” 中華民國發明專利，第192239號，專利期間:92年12月1日~95年11月30日.
23.
林泓均、陳囿全、林心蕾、張振豪, “可處理雙輸入信號的管線式傅利葉轉換系統,” 中華民國發明專利，第I254215號，專利期間:95年5月1日~98年4月30日.
24.
陳南璋、林泓均、江文榮, “具可調式電感之半導體封裝件及其承載件,” 中華民國發明專利，第I237887號，專利期間:94年8月11日~113年9月28日.
25.
陳南璋、林泓均、江文榮, “具可調式電感之半導體封裝件,” 中華民國發明專利，第I254424號，專利期間:95年5月1日~113年8月17日.
26.
陳南璋、林泓均、江文榮, “高電性之半導體封裝件及其製法,” 中華民國發明專利，第I249229號，專利期間:95年2月11日~113年3月10日.
Back