1.

Ching-Yuan Yang, Hao-Cheng Hsu, Ping-Heng Wu, Samuel Palermo, “A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation,” IEEE Solid-State Circuits Letters, vol. 7, pp. 315-318, doi.https://doi.org/10.1109/LSSC.2024.3478799, 10 2024. (SCI)

2.

Ching-Yuan Yang, Charm-Ming Hu, I-Ting Chi, Minh-Quang Chau, Dung-An Wang, “Design and characterization of an accelerometer with low cross axis sensitivity,” Microelectronic Engineering, vol. 279, pp. 1-14, 07 2023. (SCI)

3.

Ching-Yuan Yang, Chun-Hung Lin, R. C.-H. Chang, S. Palermo, “A 17.5-to-21-GHz Current-Folding Frequency Tripler With >36-dBc Harmonic Rejec-tion in 90-nm CMOS,” IEEE Solid-State Circuits Letters, vol. 6, pp. 77-80, 04 2023. (SCI)

4.

Ching-Yuan Yang, Yen-Kuei Lu, Miao-Shan Li, Tai-Yuan Chen, Chin-Lung Lin, “A 2.7-Gb/s CDR Circuit Based on Multiplexed Recirculating Delay-Locked Loop for ±10%-SSC Clock-Embedded Display Interface,” IEEE Solid-State Circuits Letters, vol. 5, pp. 94-97, 05 2022. (SCI)

5.

Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang, “A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 29, pp. 1883-1894, 05 2021. (SCI)

6.

Miao-Shan Li, Yen-Chen Lin, Chai-Chi Liu, Ching-Rong Chang, Jyun-Yi Li, You-Sheng Lin, and Ching-Yuan Yang, “A 3-Gb/s Equalizer with an Adaptive Swing Controller for TFT-LCD Interfaces,” Journal of Semiconductor Technology and Science (JSTS), vol. 1, no. 19, pp. 1-7, 05 2019. (SCI)

7.

Hsuan-Yu Chang, Ching-Yuan Yang, “A Reference Voltage Interpolation Based Calibration Method for Flash ADCs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 24, pp. 1728-1738, 05 2016. (SCI)

8.

Jung-Mao Lin, Ching-Yuan Yang, “A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment,” IEEE Transactions on Circuits and Systems-I: Regular Paper, vol. 10, no. 62, pp. 2411-2422, 10 2015. (EI、SCI)

9.

Jung-Mao Lin, Ching-Yuan Yang, Hsin-Ming Wu, “A 2.5 Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4X Oversampling,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 4, no. 23, pp. 791-795, 04 2015. (EI、SCI)

10.

Yu-Hsin Chang, Yen-Chung Chiang, Ching-Yuan Yang, “A 42.15–68.35 dBX Tunable Gain Transimpedance Amplifier Using 0.18-μm CMOS Process,” Microwave and Optical Technology Letters, vol. 4, no. 57, pp. 830-832, 04 2015. (EI、SCI)

11.

Yu-Hsin Chang, Yen-Chung Chiang, Ching-Yuan Yang, “A V-Band Push-Push VCO with Wide Tuning Range Using 0.18 μm CMOS Process,” IEEE Microwave and Wireless Components Letters, vol. 2, no. 25, pp. 115-117, 02 2015. (EI、SCI)

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

23.

24.

Ching-Yuan Yang, Chih-Hsiang Chang, “A 0.13-um CMOS 17-GHz Differential- Controlled Varactorless LC-VCO,” Journal of Engineering, National Chung Hsing University, vol. 3, no. 18, pp. 167-174, 11 2007.

25.

26.

27.

28.

29.

Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, “A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle,” IEEE J. Solid-State Circuits, vol. 8, no. 37, pp. 1021-1207, 08 2002. (EI、SCI)

30.

June-Ming Hsu, Guang-Kaai Dehng, Ching-Yuan Yang, Chu-Yuan Yang and Shen-Iuan Liu, “Low-Voltage CMOS Frequency Synthesizer for ERMES Pager Application,” IEEE Trans. on Circuits and System II, vol. 9, no. 18, pp. pp826-834, 09 2001. (EI、SCI)

31.

Ching-Yuan Yang and Shen-Iuan Liu, “A One-Wire Approach for Skew Compensating Clock Distribution Based on Bidirectional Techniques,” IEEE J. Solid-State Circuits, vol. 2, no. 36, pp. 266-272, 02 2001. (EI、SCI)

32.

Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang and Shen-Iuan Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 8, no. 35, pp. 1128-1136, 10 2000. (EI、SCI)

33.

Ching-Yuan Yang and Shen-Iuan Liu, “Fast-Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector,” IEEE J. Solid-State Circuits, vol. 10, no. 35, pp. 1445-1452, 10 2000. (EI、SCI)

34.

Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu, and Shen-Iuan Liu, “A 900-MHz/1-V CMOS Frequency Synthesizer,” IEEE J. Solid-State Circuits, vol. 8, no. 35, pp. 1211-1214, 08 2000. (EI、SCI)

35.

Ching-Yuan Yang, Guang-Kaai Dehng, J. M. Hsu and Shen-Iuan Liu, “New Dynamic Flip-Flops for High-Speed Dual-Modulus Prescaler ,” IEEE J. Solid-State Circuits, vol. 10, no. 33, pp. 1568-1571, 10 1998. (EI、SCI)

36.

Shen-Iuan Liu and Ching-Yuan Yang, “High-Input Impedance Filters Using Two FTFNs,” Int. J. Electronics, no. 84, pp. 595-598, 06 1998.

37.

Ching-Yuan Yang, Guang-Kaai Dehng and Shen-Iuan Liu, “High-Speed Divide-by-4/5 Counter for a Dual-Modulus Prescaler,” Electronics Letters, no. 33, pp. 1691-1692, 09 1997. (EI、SCI)

38.

Shen-Iuan Liu and Ching-Yuan Yang, “Higher-Order Immittance Function Synthesis Using CCIIIs,” Electronics Letters, no. 32, pp. 2295-2296, 12 1996. (EI、SCI)

1.

Ching-Yuan Yang and Chun-Hung Lin, “A Fractional Frequency Divider Using Pipelined Phase Interpolation Compen-sation Technology,” The 10th Taiwan and Japan Conference on Circuits and Systems (TJCAS 2024), 08 2024. Japan,

2.

Shu-Chi Wang, Ching-Yuan Yang, “Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector,” International SoC Design Conference (ISOCC 2023), 10 2023. Korea,

3.

Wan-Yu You, Ching-Yuan Yang, “Behavior Simulation of SSC Generator With Adjustable Modulation Frequency and Depth,” International SoC Design Conference (ISOCC 2023), 10 2023. Korea,

4.

Chun-Hung Lin, Ching-Yuan Yang, “A 17-21GHz Current-Folding Frequency Tripler With >36dBc Harmonic Rejection in 90nm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC 2022), 11 2022. Taiwan,

5.

Tsung-Ying Chen, Ching-Yuan Yang, Dung-An Wang, “A 80-MHz 91.2 ppm/°C Self-Biased Frequency-Locked-Loop Timer,” International SoC Design Conference (ISOCC 2022), 10 2022. Korea,

6.

Shao-Yu Shu, Chun-Hun Lin, Ching-Yuan Yang, “A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 04 2022. Taiwan,

7.

Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin, “A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth,” IEEE Asian Solid-State Circuits Conference (A-SSCC), 11 2021. Korea,

8.

Yong-Zheng Wang, Ching-Yuan Yang, “A Self Synchronized-Switch Rectifier for Piezoelectric-Vibration Energy-Harvesting Systems,” International SoC Design Conference (ISOCC), 10 2021. Korea,

9.

Hao-Hsiang Hsu, Ching-Yuan Yang, Dung-An Wang, “A High-Efficiency Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting,” International SoC Design Conference (ISOCC), 10 2020. Korea,

10.

Wan-Ling Wu, Ching-Yuan Yang, Dung-An Wang, “A Flipping Active-Diode Rectifier for Piezoelectric-Vibration Ener-gy-Harvesting,” European Conference on Circuit Theory and Design (ECCTD), 09 2020. Sofia, Bulgaria,

11.

Po-Yu Hsieh, Shao-Yu Shu, and Ching-Yuan Yang, “A Spur-Suppression Technique for Frequency Synthesizer With Pulse-Width to Current Conversion,” International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 12 2019. Taiwan,

12.

Miao-Shan Li, Yen-Kuei Lu, Ching-Yuan Yang, and Chin-Lung Lin, “PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems,” International SoC Design Conference (ISOCC), 10 2019. Korea,

13.

Wan-Ling Wu, Yong-Zheng Wang and Ching-Yuan Yang, “Flipping Rectifiers for Piezoelectric Vibration Energy Harvesting,” International SoC Design Conference (ISOCC), 10 2019. Korea,

14.

You-Sheng Lin, Miao-Shan Li and Ching-Yuan Yang, “A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL,” IEEE International System-on-Chip Conference (SOCC), 09 2019. Singapore,

15.

Guan-Min Luo and Ching-Yuan Yang, “A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection,” IEEE International System-on-Chip Conference (SOCC), 09 2019. Singapore,

16.

Chih-Wei Tsai, Ching-Yuan Yang, “A Low-Noise All-Digital Frequency Synthesizer Using PVT-Tolerable Low-Gain-Error Time Amplifier,” The 25th VLSI Design/CAD Symposium, 08 2015. Taiwan,

17.

Po-Tsang Chen, Ching-Yuan Yang, “A 43.8-51.3 GHz Frequency Synthesizer with an Injection-Lock Frequency Tri-pler,” The 25th VLSI Design/CAD Symposium, 08 2015. Taiwan,

18.

Ching-Yuan Yang, Guan-Wei Chen, Po-Tsang Chen, Jun-Hong Weng, “A Frequency Synthesizer With an Injection Lock Oscillator for Wireless Com-munications,” 2015 International Conference on Electrical and Electronics: Techniques and Applications (EETA2015), 08 2015. Thailand,

19.

Guan-Wei Chen, Ching-Yuan Yang, “Frequency Synthesizer for 60-GHz Wireless Communication Systems,” VLSI Design/CAD Symposium, 08 2014. Taiwan,

20.

Wei-Chao Huang, Ching-Yuan Yang, “An All-Digital Frequency Synthesizer for IEEE 802.11ad Channels,” VLSI Design/CAD Symposium, 08 2014. Taiwan,

21.

Hsuan-Yu Chang, Ching-Yuan Yang, “A High-Speed Low-Power Calibrated Flash ADC,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2369-2372, 06 2014. (EI)Melbourne, Australia,

22.

Chih-Hsiang Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, Nai-Chen Cheng, “A 3.4mW 2.3-to-2.7GHz Frequency Synthesizer in 0.18-um CMOS,” European Solid-State Circuits Conference (ESSCIRC 2013), pp. 53-56, 09 2013. (EI)Bucharest, Romania,

23.

Ching-Yuan Yang, Chih-Hsiang Chang, “A 35-GHz Frequency Synthesizer Using Frequency Doubling and Phase Ro-tating Technology,” International Symposium on Communications and Information Technolo-gies (ISCIT), pp. 266-270, 09 2013. (EI)Thailand,

24.

Jun-Hong Weng, Yun-Chu Lee, Ching-Yuan Yang, “A SIDO DC-DC Converter With Variable Controlled Outputs,” VLSI Design/CAD Symposium, 08 2013. Taiwan,

25.

Hsuan-Chiang Hsu, Ching-Yuan Yang, “A Frequency Synthesizer for 60-GHz Communication Systems,” VLSI Design/CAD Symposium, 08 2013. Taiwan,

26.

Ching-Yuan Yang, Jia-Jiun Lin, Chih-Hsiang Chang, “A 22-GHz Low-Power Frequency Synthesizer in 0.18-um CMOS,” International Symposium on Communications and Information Technolo-gies (ISCIT), pp. 123-126, 10 2012. (EI)Gold Coast, Australia,

27.

Jia-Jiun Lin, Ching-Yuan Yang, “A 22/11-GHz Frequency Synthesizer in 0.18-um CMOS,” The 23th VLSI Design/CAD Symposium, 08 2012. Taiwan,

28.

Ai-Jia Chuang, Yu Lee, Ching-Yuan Yang, “A Chip-to-Chip Clock-Deskewing Circuit for 3-D ICs,” IEEE International Symposium on Circuits and Systems (ISCAS 2012), pp. 1652-1655, 05 2012. (EI)Seoul, Korea,

29.

Hsin-Ta Yang, Ching-Yuan Yang, “EMI Reduction by Spread-Spectrum Modulation in PWM Converters,” The 22th VLSI Design/CAD Symposium, 08 2011. Taiwan,

30.

Ai-Jia Chuang, Ching-Yuan Yang, “Design of a Clock-Deskew Buffer Circuit for Chip-to-Chip Links,” The 22th VLSI Design/CAD Symposium, 08 2011. Taiwan,

31.

Jun-Hong Weng, Ching-Yuan Yang, Yi-Lin Jhu, “A Low-Power Direct Digital Frequency Synthesizer Using an Analogue-Sine-Conversion Technique,” International Symposium on Low Power Electronics and Design (ISLPED), pp. 193-197, 08 2011. (EI)Fukuoka, Japan,

32.

Ching-Yuan Yang, Wei-Shuo Lin, Jung-Mao Lin, Hsin-Ming Wu, “A 2.5-Gb/s Clock and Data Recovery Circuit With DeltaSimga-Modulated Fractional Frequency Compensation,” IEEE TENCON, 11 2010. (EI)Japan,

33.

Chung-Wei Su, Hsuan-Yu Chang, Ching-Yuan Yang, “A 6-bit 1-GS/s Pipelined Analog-to-Digital Converter With Open-Loop Residue Amplifiers,” The 21th VLSI Design/CAD Symposium, 08 2010. Taiwan,

34.

Jun-Hong Weng, Yi-Lin Jhu, Ching-Yuan Yang, “A 1.5-GHz Low-Power CMOS ROM-less Direct Digital Frequency Synthesizer,” The 21th VLSI Design/CAD Symposium, pp. 545-548, 08 2010. Taiwan,

35.

Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen, “An Embedded Wide-Range and High-Resolution CLOCK Jitter Measurement Circuit,” Design, Automation & Test in Europe (DATE), 03 2010. (EI)Germany,

36.

Ching-Yuan Yang, Hsin-Ming Wu, Jun-Hong Weng, Ping-Heng Wu, “A Wide-Range Frequency Synthesizer Using a Compensated Phase-Rotating Technique for Digital TV Tuners,” 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2009), pp. 397-400, 12 2009. (EI)Japan,

37.

Ching-Yuan Yang, Hsuan-Yu Chang, “A 4-GS/s 6-bits Flash ADCWith a Resistor Regulator for Offset Cancellation,” The 20th VLSI Design/CAD Symposium, 08 2009. Taiwan,

38.

Ching-Yuan Yang, Wei-Shuo Lin, “A 2.5-Gb/s Clock and Data Recovery Circuit Using Oversampling and Frequency-Calibrated Techniques,” The 20th VLSI Design/CAD Symposium, 08 2009. Taiwan,

39.

Chih-Hsiang Chang, Ching-Yuan Yang, “A Low-Voltage, 9-GHz, 0.13-um CMOS Frequency Synthesizer With a Fractional Phase-Rotating and Frequency-Doubling Topology,” 2009 Symposium on VLSI Circuits, pp. 192-193, 06 2009. (EI)Kyoto,

40.

Kai Pong Wu, Ching-Yuan Yang, Jung-Mao Lin, “A 2.5Gb/s Oversampling Clock and Data Recovery Circuit with Frequency Calibration Technique,” IEEE Asia Pacific Conference on Circuits and Systems, pp. 1356-1359, 12 2008. (EI)Macao,

41.

Gung-Yu Lin, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, “A Programmable Duty Cycle Corrector Based on Delta-Sigma Modulated PWM Mechanism,” IEEE Asia Pacific Conference on Circuits and Systems, pp. 1406-1409, 12 2008. (EI)Macao,

42.

Chih-Hsiang Chang, Po-Vu Chen, Ching-Yuan Yang, “Doubled Sampling 100-MS/s 10-Bit Fully Differential Pipeline Analog to Digital Converter,” VLSI Design/CAD Symposium, 08 2008. Kenting, Taiwan,

43.

Chih-Hsiang Chang, Ching-Yuan Yang, “A Low-Voltage High-Frequency CMOS LC-VCO Using a Transformer Feedback,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 545-548, 06 2008. (EI)Atlanta,

44.

Chih-Hsiang Chang, Chih-Yi Hsiao, Ching-Yuan Yang, “A 1-GS/s CMOS 6-bit Flash ADC with an Offset Calibrating Method,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 232-235, 04 2008. (EI)Taiwan,

45.

Soul-Yu Chao, Ching-Yuan Yang, “A 2.4-GHz 0.18-μm CMOS Doubly Balanced Mixer with High Linearity,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 247-250, 04 2008. (EI)Taiwan,

46.

Meng-Ting Tsai, Ching-Yuan Yang, “A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-Mode WiFi/WiMAX Applications,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1384-1387, 12 2007. (EI)Morocco,

47.

Jun-Hong Weng, Ching-Yuan Yang, “An Active Gm-C Filter Using a Linear Transconductance,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 909-912, 12 2007. (EI)Taiwan,

48.

Tsung-Chan Wu, Ching-Yuan Yang, “A Transformer-Feedback Quadrature Voltage-Controlled Oscillator Using a Transconductance Tuning Technique,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 449-452, 12 2007. (EI)Taiwan,

49.

Chih-Hsiang Chang, Ching-Yuan Yang, “A 0.18-um CMOS 16-GHz Varactorless LC-VCO with 1.2-GHz Tuning Range,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 107-110, 11 2007. (EI)Korea,

50.

Jun-Hong Weng, Jing-Shing Wen, Chiing-Yuan Yang, “A High-Speed ROM-less Direct Digital Frequency Synthesizer Realized by a Segmented Non-linear DAC,” Proc. IEEE TENCON, 10 2007. (EI)Taipei, Taiwan,

51.

Kai-Pong Wu, Ching-Yuan Yang, Hsin-Ming Wu, Jung-Mao Lin, “A 3.125-Gb/s Burst-Mode Clock and Data Recovery Circuit With a Data-Injection Oscillator Using Half Rate Clock Techniques,” Proc. IEEE TENCON, 10 2007. (EI)Taipei, Taiwan,

52.

Ping-Heng Wu, Ching-Yuan Yang, So-Yu Chao, “A Wide-Band PLL-Based Frequency Synthesizer with Adaptive Dynamics,” Proc. IEEE TENCON, 10 2007. (EI)Taipei, Taiwan,

53.

Chih-Hsiang Chang, Ching-Yuan Yang , “A 8-bit 150-MS/s Fully Differential Dual-channel Time-interleaved Pipeline A/D Converter,” Proc. 18th VLSI Design/CAD Symp., pp. 363-366 , 08 2007. Taiwan,

54.

Chia-Chieh Tu, Ching-Yuan Yang, “A 6.5-GHz LC VCO with Integrated-Transformer Tuning,” Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 511-514, 12 2006. (EI)

55.

Hsin-Ming Wu, Ching-Yuan Yang, “A 3.125-GHz Limiting Amplifier for Optical Receiver System,” Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 210-213, 12 2006. (EI)

56.

Te-Ming Tseng, Hsin-Ming Wu, Ching-Yuan Yang, “A 3.125-Gb/s Laser Driver Using a Dual-Loop Control for Optical Transmitters,” Proc. 17th VLSI Design/CAD Symp., pp. 645-648, 08 2006. Taiwan,

57.

Ken-Hao Chang, Kai-Pong Wu, Ching-Yuan Yang, “A Half-Rate Clock and Data Recovery Circuit with a Phase-Realignment Oscillator,” Proc. 17th VLSI Design/CAD Symp., pp. 129-132, 08 2006. Taiwan,

58.

Wen-Ger Wong, Chia-Chieh Tu, Ching-Yuan Yang, “A Spread-Spectrum Clock Generator Using Phase-Compensation Fractional PLL,” Proc. 17th VLSI Design/CAD Symp., pp. 121-124, 08 2006. Taiwan,

59.

Ming-Bin Chen, Ching-Yuan Yang, Meng-Ting Tsai, “A Fractional-N Frequency Synthesizer with a Ripple-Suppressed Loop Filter for IEEE 802.11a/b/g Channels,” Proc. 17th VLSI Design/CAD Symp., pp. 113-116, 08 2006. Taiwan,

60.

Jun-Hong Weng, Chong-Jng Yu, Ching-Yuan Yang, and Peng-Chang Yang, “A Low-Noise Microsensor Amplifier with Automatic Gain Control System,” Proc. IEEE International Symposium on Circuits and Systems, pp. 1410-1413, 05 2006. (EI)

61.

Meng-Ting Tsai and Ching-Yuan Yang, “A Frequency Synthesizer Realized by a Transformer-Based Voltage-Controlled Oscillator for IEEE 802.11a/b/g Channels,” Proc. IEEE International Symposium on Circuits and Systems, pp. 5199-5202, 05 2006. (EI)

62.

Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, and Ching-Yuan Yang, “A 1.8-Gb/s Burst-Mode Clock and Data Recovery Circuit with a 1/4-Rate Clock Technique,” Proc. IEEE International Symposium on Circuits and Systems, pp. 3073-3076, 05 2006. (EI)

63.

Ching-Yuan Yang, Chih-Hsiang Chang,, “A Low-Power 8-bit 200-Ms/s Fully Differential CMOS Pipeline A/D Converter,” VLSI/CAD Symposium, 08 2005. Taiwan,

64.

Ching-Yuan Yang, Meng-Ting Tsai, Wen-Ger Wong, “A CMOS Continuous-Time Gm-C Low Pass Filter With On-Chip Automatic Tuning,” VLSI/CAD Symposium, 08 2005. Taiwan,

65.

Ching-Yuan Yang, Ken-Hao Chang, Jung-Mao Lin, and Te-Ming Tseng, “A 12-MHz Voltage/Temperature Independent Frequency Generator,” VLSI/CAD symposium, 08 2005. Taiwan,

66.

Ching-Yuan Yang and Yu Lee, “A 0.18-um CMOS 1-Gb/s Serial Link Transceiver by Using PWM and PAM Techniques,” Proc. IEEE International Symposium on Circuits and Systems, pp. 1150-1153, 05 2005. (EI)

67.

Ching-Yuan Yang, Jen-Wen Chen and Meng-Ting Tsai, “A High-Frequency Phase-Compensation Fraction-N Frequency Synthesizer,” Proc. IEEE International Symposium on Circuits and Systems, pp. 5091-5094, 05 2005. (EI)

68.

Ching-Yuan Yang, Jen-Wen Chen and Kuei-Zu Jiang, “A 1.6-GHz Delta-Sigma Modulated Fractional-N Frequency Synthesizer,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-DAT), pp. 157-160, 04 2005. (EI)Taiwan,

69.

Ching-Yuan Yang, Yu Lee and Cheng-Hsing Lee, “A 1.25Gb/s Half-Rate Clock and Data Recovery Circuit,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-DAT), pp. 116-119, 04 2005.

70.

Ching-Yuan Yang, Cheng-Hsing Lee and Yu Lee, “A 1.25Gb/S Clock and Data Recovery Circuit Using Half Rate Clock Technique,” Applied Science and Technology Conference (ASTC)- Photonics and Communications, 12 2004.

71.

Ching-Yuan Yang and Yu Lee, “A High Speed Serial Link Transceiver,” Applied Science and Technology Conference (ASTC)- Photonics and Communications, 12 2004.

72.

Ching-Yuan Yang and Tzu-Fan Chen, “A Dual-Band 2.4GHz/5.2GHz Fully Integrated CMOS Low Noise Amplifier,” Applied Science and Technology Conference (ASTC)- Photonics and Communications, 12 2004.

73.

Ching-Yuan Yang and Kuei-Zu Jiang, “A Channel-Selecting Fractional-N Frequency Synthesizer for IEEE 802.11b Standard,” The 15th VLSI/CAD symposium, 08 2004. Taiwan, R.O.C.,

74.

Ching-Yuan Yang and Cheng-Hsing Lee, “A 1.25GB/S Clock and Data Recovery Circuit for Random Non-Return-to-Zero Data,” The 15th VLSI/CAD symposium, 08 2004. Taiwan, R.O.C.,

75.

Yi-Zhen Huang, and Ching-Yuan Yang, “Dual-Loop Delay-Locked Loop for Duty-Cycle Adjustment,” The 13th VLSI/CAD symposium, 08 2002. Taiwan, R.O.C.,

76.

Chun-Chuan Liu, and Ching-Yuan Yang, “Analog Direct Synchronous Mirror Delay Circuit with Delay-Locked Loop for ASIC,” The 13th VLSI/CAD symposium, 08 2002. Taiwan, R.O.C.,

77.

Chia-Yang Chang, Po-Chang Chen, Ching-Yuan Yang, Yang-Han Lee, “The CMOS on-chip oscillator based on level tracking technique,” Proc. IEEE Asia-Pacific Conference on ASICs, pp. 197 –200, 2002.

78.

J. M. Hsu, Shen-Iuan Liu, Ching-Yuan Yang, and G. K. Dehng, “A 1 V CMOS Dynamic Back-Gate Forward Bias Prescaler for Frequency Synthesizer Application,” 1999 Analog VLSI Workshop, pp. 45-50, 1999.

79.

Ching-Yuan Yang, J. M. Hsu and Shen-Iuan Liu, “A 4-GHz CMOS Dual-Modulus Prescaler with High-Speed Dynamic Flip-Flops ,” The 9th VLSI/CAD symposium, pp. 203-206, 08 1998. Taiwan, R.O.C.,

80.

Ching-Yuan Yang, Wang-Chih and Shen-Iuan Liu, “Effectively Reduced Pull-in Time of PLL with Nonlinear Phase Comparator,” The 8th VLSI/CAD symposium, pp. 205-208, 08 1997. Taiwan, R.O.C.,

81.

Shen-Iuan Liu, Chih-Feng Lin, and Ching-Yuan Yang, “A PLL-Based Programmable Clock Generator with 15 to 180-MHz Lock Range,” The 7th VLSI/CAD symposium, pp. 151-154, 08 1996. Taiwan, R.O.C.,

1.

劉深淵、楊清淵, “鎖相迴路,” 滄海書局, 11 2006.

1.

Chih-Hsiang Chang, Jung-Mao Lin, Ching-Yuan Yang, “Frequency Doubler,” United States Patent Application Publication, Pub. No: US 2011/0175651 A1, 07 2011.

2.

Chih-Hsiang Chang, Jung-Mao Lin, Ching-Yuan Yang, “Voltage Controlled Oscillator,” United States Patent Application Publication, Pub. No: US 2011/0018645 A1, 01 2011.

3.

Ching-Yuan Yang, Jung-Mao Lin, Yu-Min Lin, “Bust-Mode Clock And Data Recovery Circuit Using Phase Selecting Technology,” United States Patent Application Publication, Pub. No: US 2010/0040182 A1, 02 2010.

4.

Chia-Yang Chang, Po-Chang Chen, Yang-Han Lee, Ching-Yuan Yang, “Digital Adjustable Chip Oscillator,” US Patent No. 7002414 B2, 02 2006.

5.

張佳陽、陳柏璋、李揚漢、楊清淵, “數位可調式晶片振盪器,” 中華民國專利，發明第197975號，自民國93年2月21日起至民國111年11月7止.

6.

劉深淵、楊清淵, “利用單一導線補償時脈信號誤差之方法及電路,” 中華民國專利，發明第165962號，自民國91年10月21日起至民國110年1月11止.

7.

李其健、楊清淵、鄧光鎧、許峻銘、劉深淵, “快速動態式正反器,” 中華民國專利，發明第169564號，自民國90年2月21日起至民國100年10月28日止.

8.

Ching-Yuan Yang, Shen-Iuan Liu and Liang-Gee Chen, “High-Frequency CMOS Dual/Multi-Modulus Prescaler,” US Patent No. 6094466, from Jul. 25, 2000 to Jan. 10, 2017.

9.

楊清淵、劉深淵, “除4/5電路,” 中華民國專利，發明第107136號，自民國88年8月21日起至民國106年10月1日止.

10.

Ching-Yuan Yang, Shen-Iuan Liu, “Divide-by-4/5 counter,” US Patent No. 5930322, from Jul. 27, 1999 to Oct. 28, 2017.

11.

楊清淵、劉深淵、陳良基, “高頻互補式金氧半雙模/多模前置分頻器,” 中華民國專利，發明第114359號，自民國89年4月11日起至民國105年9月22日止.