師資介紹 系統晶片組
  1. 師資介紹
  2. Professor
 
  1. 系統晶片組
 
  1. 楊清淵Ching-Yuan Yang
  2.  
        1. 職稱
        2. 教授
        1. 學歷
        2. 國立台灣大學電機工程博士
        1. 電話
        2. 886-4-22851549-823
        1. 電子信箱
        2. ycy@dragon.nchu.edu.tw
  3. 重要經歷
  4. 國立中興大學電機工程學系 教授 (現在)
    國立中興大學電機工程學系 副教授
    國立中興大學電機工程學系 助理教授
    華梵大學電子工程學系 助理教授
    國立台灣大學電機工程學系 專任助教
    工研院資通所 顧問
    大同公司電腦開發處 工程師
  5.  
  6. 研究領域
  7. 類比、射頻、混合信號積體電路設計
  8.  
  9. 學術服務
  10. 教育部科技顧問室智慧電子總聯盟辦公室-前瞻教學平台(ATP)辦公室、教育部智慧聯網技術與應用人才培育計畫-智慧聯盟整合推動聯盟中心之「課程資料庫系統」和「非同步課程資料庫系統」負責教師
    VLSI Design/CAD Symposium, Taiwan, TPC (technical program committee)
    IEEE Asian Solid-State Circuits Conference (A-SSCC) TPC (2016~2021),Section Chair
  11.  
  12. 榮譽獎勵
  13. 目前無榮譽獎勵
  14.  
  15. 著作目錄
    1. A.期刊論文
      1. 1.
      2. Ching-Yuan Yang, Yen-Kuei Lu, Miao-Shan Li, Tai-Yuan Chen, Chin-Lung Lin, “A 2.7-Gb/s CDR Circuit Based on Multiplexed Recirculating Delay-Locked Loop for ±10%-SSC Clock-Embedded Display Interface,” IEEE Solid-State Circuits Letters, vol.5, pp.94-97, May 2022. (SCI)
      1. 2.
      2. Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang, “A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.29, no.5, pp.1883-1894, May 2021. (SCI)
      1. 3.
      2. Miao-Shan Li, Yen-Chen Lin, Chai-Chi Liu, Ching-Rong Chang, Jyun-Yi Li, You-Sheng Lin, and Ching-Yuan Yang, “A 3-Gb/s Equalizer with an Adaptive Swing Controller for TFT-LCD Interfaces,” Journal of Semiconductor Technology and Science (JSTS), vol.19, no.1, pp.1-7, May 2019. (SCI)
      1. 4.
      2. Hsuan-Yu Chang, Ching-Yuan Yang, “A Reference Voltage Interpolation Based Calibration Method for Flash ADCs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.5, pp.1728-1738, May 2016. (SCI)
      1. 5.
      2. Jung-Mao Lin, Ching-Yuan Yang, “A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment,” IEEE Transactions on Circuits and Systems-I: Regular Paper, vol.62, no.10, pp.2411-2422, October 2015. (SCI、EI)
      1. 6.
      2. Yu-Hsin Chang, Yen-Chung Chiang, Ching-Yuan Yang, “A 42.15–68.35 dBX Tunable Gain Transimpedance Amplifier Using 0.18-μm CMOS Process,” Microwave and Optical Technology Letters, vol.57, no.4, pp.830-832, April 2015. (SCI、EI)
      1. 7.
      2. Jung-Mao Lin, Ching-Yuan Yang, Hsin-Ming Wu, “A 2.5 Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4X Oversampling,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.23, no.4, pp.791-795, April 2015. (SCI、EI)
      1. 8.
      2. Yu-Hsin Chang, Yen-Chung Chiang, Ching-Yuan Yang, “A V-Band Push-Push VCO with Wide Tuning Range Using 0.18 μm CMOS Process,” IEEE Microwave and Wireless Components Letters, vol.25, no.2, pp.115-117, February 2015. (SCI、EI)
      1. 22.
      2. Ching-Yuan Yang, Chih-Hsiang Chang, “A 0.13-um CMOS 17-GHz Differential- Controlled Varactorless LC-VCO,” Journal of Engineering, National Chung Hsing University, vol.18, no.3, pp.167-174, November 2007.
      1. 26.
      2. Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, “A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle,” IEEE J. Solid-State Circuits, vol.37, no.8, pp.1021-1207, August 2002. (SCI、EI)
      1. 27.
      2. June-Ming Hsu, Guang-Kaai Dehng, Ching-Yuan Yang, Chu-Yuan Yang and Shen-Iuan Liu, “Low-Voltage CMOS Frequency Synthesizer for ERMES Pager Application,” IEEE Trans. on Circuits and System II, vol.18, no.9, pp.pp826-834, September 2001. (SCI、EI)
      1. 28.
      2. Ching-Yuan Yang and Shen-Iuan Liu, “A One-Wire Approach for Skew Compensating Clock Distribution Based on Bidirectional Techniques,” IEEE J. Solid-State Circuits, vol.36, no.2, pp.266-272, February 2001. (SCI、EI)
      1. 29.
      2. Ching-Yuan Yang and Shen-Iuan Liu, “Fast-Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector,” IEEE J. Solid-State Circuits, vol.35, no.10, pp.1445-1452, October 2000. (SCI、EI)
      1. 30.
      2. Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang and Shen-Iuan Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol.35, no.8, pp.1128-1136, October 2000. (SCI、EI)
      1. 31.
      2. Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu, and Shen-Iuan Liu, “A 900-MHz/1-V CMOS Frequency Synthesizer,” IEEE J. Solid-State Circuits, vol.35, no.8, pp.1211-1214, August 2000. (SCI、EI)
      1. 32.
      2. Ching-Yuan Yang, Guang-Kaai Dehng, J. M. Hsu and Shen-Iuan Liu, “New Dynamic Flip-Flops for High-Speed Dual-Modulus Prescaler ,” IEEE J. Solid-State Circuits, vol.33, no.10, pp.1568-1571, October 1998. (SCI、EI)
      1. 33.
      2. Shen-Iuan Liu and Ching-Yuan Yang, “High-Input Impedance Filters Using Two FTFNs,” Int. J. Electronics, vol.84, pp.595-598, June 1998.
      1. 34.
      2. Ching-Yuan Yang, Guang-Kaai Dehng and Shen-Iuan Liu, “High-Speed Divide-by-4/5 Counter for a Dual-Modulus Prescaler,” Electronics Letters, vol.33, pp.1691-1692, September 1997. (SCI、EI)
      1. 35.
      2. Shen-Iuan Liu and Ching-Yuan Yang, “Higher-Order Immittance Function Synthesis Using CCIIIs,” Electronics Letters, vol.32, pp.2295-2296, December 1996. (SCI、EI)
    2. B.研討會論文
      1. 1.
      2. Shao-Yu Shu, Chun-Hun Lin, Ching-Yuan Yang, “A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Taiwan, April 2022.
      1. 2.
      2. Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin, “A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Korea, November 2021.
      1. 3.
      2. Yong-Zheng Wang, Ching-Yuan Yang, “A Self Synchronized-Switch Rectifier for Piezoelectric-Vibration Energy-Harvesting Systems,” International SoC Design Conference (ISOCC), Korea, October 2021.
      1. 4.
      2. Hao-Hsiang Hsu, Ching-Yuan Yang, Dung-An Wang, “A High-Efficiency Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting,” International SoC Design Conference (ISOCC), Korea, October 2020.
      1. 5.
      2. Wan-Ling Wu, Ching-Yuan Yang, Dung-An Wang, “A Flipping Active-Diode Rectifier for Piezoelectric-Vibration Ener-gy-Harvesting,” European Conference on Circuit Theory and Design (ECCTD), Sofia, Bulgaria, September 2020.
      1. 6.
      2. Po-Yu Hsieh, Shao-Yu Shu, and Ching-Yuan Yang, “A Spur-Suppression Technique for Frequency Synthesizer With Pulse-Width to Current Conversion,” International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Taiwan, December 2019.
      1. 7.
      2. Wan-Ling Wu, Yong-Zheng Wang and Ching-Yuan Yang, “Flipping Rectifiers for Piezoelectric Vibration Energy Harvesting,” International SoC Design Conference (ISOCC), Korea, October 2019.
      1. 8.
      2. Miao-Shan Li, Yen-Kuei Lu, Ching-Yuan Yang, and Chin-Lung Lin, “PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems,” International SoC Design Conference (ISOCC), Korea, October 2019.
      1. 9.
      2. Guan-Min Luo and Ching-Yuan Yang, “A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection,” IEEE International System-on-Chip Conference (SOCC), Singapore, September 2019.
      1. 10.
      2. You-Sheng Lin, Miao-Shan Li and Ching-Yuan Yang, “A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL,” IEEE International System-on-Chip Conference (SOCC), Singapore, September 2019.
      1. 11.
      2. Ching-Yuan Yang, Guan-Wei Chen, Po-Tsang Chen, Jun-Hong Weng, “A Frequency Synthesizer With an Injection Lock Oscillator for Wireless Com-munications,” 2015 International Conference on Electrical and Electronics: Techniques and Applications (EETA2015), Thailand, August 2015.
      1. 12.
      2. Po-Tsang Chen, Ching-Yuan Yang, “A 43.8-51.3 GHz Frequency Synthesizer with an Injection-Lock Frequency Tri-pler,” The 25th VLSI Design/CAD Symposium, Taiwan, August 2015.
      1. 13.
      2. Chih-Wei Tsai, Ching-Yuan Yang, “A Low-Noise All-Digital Frequency Synthesizer Using PVT-Tolerable Low-Gain-Error Time Amplifier,” The 25th VLSI Design/CAD Symposium, Taiwan, August 2015.
      1. 14.
      2. Wei-Chao Huang, Ching-Yuan Yang, “An All-Digital Frequency Synthesizer for IEEE 802.11ad Channels,” VLSI Design/CAD Symposium, Taiwan, August 2014.
      1. 15.
      2. Guan-Wei Chen, Ching-Yuan Yang, “Frequency Synthesizer for 60-GHz Wireless Communication Systems,” VLSI Design/CAD Symposium, Taiwan, August 2014.
      1. 16.
      2. Hsuan-Yu Chang, Ching-Yuan Yang, “A High-Speed Low-Power Calibrated Flash ADC,” IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, pp.2369-2372, June 2014. (EI)
      1. 17.
      2. Ching-Yuan Yang, Chih-Hsiang Chang, “A 35-GHz Frequency Synthesizer Using Frequency Doubling and Phase Ro-tating Technology,” International Symposium on Communications and Information Technolo-gies (ISCIT), Thailand, pp.266-270, September 2013. (EI)
      1. 18.
      2. Chih-Hsiang Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, Nai-Chen Cheng, “A 3.4mW 2.3-to-2.7GHz Frequency Synthesizer in 0.18-um CMOS,” European Solid-State Circuits Conference (ESSCIRC 2013), Bucharest, Romania, pp.53-56, September 2013. (EI)
      1. 19.
      2. Hsuan-Chiang Hsu, Ching-Yuan Yang, “A Frequency Synthesizer for 60-GHz Communication Systems,” VLSI Design/CAD Symposium, Taiwan, August 2013.
      1. 20.
      2. Jun-Hong Weng, Yun-Chu Lee, Ching-Yuan Yang, “A SIDO DC-DC Converter With Variable Controlled Outputs,” VLSI Design/CAD Symposium, Taiwan, August 2013.
      1. 21.
      2. Ching-Yuan Yang, Jia-Jiun Lin, Chih-Hsiang Chang, “A 22-GHz Low-Power Frequency Synthesizer in 0.18-um CMOS,” International Symposium on Communications and Information Technolo-gies (ISCIT), Gold Coast, Australia, pp.123-126, October 2012. (EI)
      1. 22.
      2. Jia-Jiun Lin, Ching-Yuan Yang, “A 22/11-GHz Frequency Synthesizer in 0.18-um CMOS,” The 23th VLSI Design/CAD Symposium, Taiwan, August 2012.
      1. 23.
      2. Ai-Jia Chuang, Yu Lee, Ching-Yuan Yang, “A Chip-to-Chip Clock-Deskewing Circuit for 3-D ICs,” IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, pp.1652-1655, May 2012. (EI)
      1. 24.
      2. Jun-Hong Weng, Ching-Yuan Yang, Yi-Lin Jhu, “A Low-Power Direct Digital Frequency Synthesizer Using an Analogue-Sine-Conversion Technique,” International Symposium on Low Power Electronics and Design (ISLPED), Fukuoka, Japan, pp.193-197, August 2011. (EI)
      1. 25.
      2. Ai-Jia Chuang, Ching-Yuan Yang, “Design of a Clock-Deskew Buffer Circuit for Chip-to-Chip Links,” The 22th VLSI Design/CAD Symposium, Taiwan, August 2011.
      1. 26.
      2. Hsin-Ta Yang, Ching-Yuan Yang, “EMI Reduction by Spread-Spectrum Modulation in PWM Converters,” The 22th VLSI Design/CAD Symposium, Taiwan, August 2011.
      1. 27.
      2. Ching-Yuan Yang, Wei-Shuo Lin, Jung-Mao Lin, Hsin-Ming Wu, “A 2.5-Gb/s Clock and Data Recovery Circuit With DeltaSimga-Modulated Fractional Frequency Compensation,” IEEE TENCON, Japan, November 2010. (EI)
      1. 28.
      2. Jun-Hong Weng, Yi-Lin Jhu, Ching-Yuan Yang, “A 1.5-GHz Low-Power CMOS ROM-less Direct Digital Frequency Synthesizer,” The 21th VLSI Design/CAD Symposium, Taiwan, pp.545-548, August 2010.
      1. 29.
      2. Chung-Wei Su, Hsuan-Yu Chang, Ching-Yuan Yang, “A 6-bit 1-GS/s Pipelined Analog-to-Digital Converter With Open-Loop Residue Amplifiers,” The 21th VLSI Design/CAD Symposium, Taiwan, August 2010.
      1. 30.
      2. Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen, “An Embedded Wide-Range and High-Resolution CLOCK Jitter Measurement Circuit,” Design, Automation & Test in Europe (DATE), Germany, March 2010. (EI)
      1. 31.
      2. Ching-Yuan Yang, Hsin-Ming Wu, Jun-Hong Weng, Ping-Heng Wu, “A Wide-Range Frequency Synthesizer Using a Compensated Phase-Rotating Technique for Digital TV Tuners,” 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2009), Japan, pp.397-400, December 2009. (EI)
      1. 32.
      2. Ching-Yuan Yang, Wei-Shuo Lin, “A 2.5-Gb/s Clock and Data Recovery Circuit Using Oversampling and Frequency-Calibrated Techniques,” The 20th VLSI Design/CAD Symposium, Taiwan, August 2009.
      1. 33.
      2. Ching-Yuan Yang, Hsuan-Yu Chang, “A 4-GS/s 6-bits Flash ADCWith a Resistor Regulator for Offset Cancellation,” The 20th VLSI Design/CAD Symposium, Taiwan, August 2009.
      1. 34.
      2. Chih-Hsiang Chang, Ching-Yuan Yang, “A Low-Voltage, 9-GHz, 0.13-um CMOS Frequency Synthesizer With a Fractional Phase-Rotating and Frequency-Doubling Topology,” 2009 Symposium on VLSI Circuits, Kyoto, pp.192-193, June 2009. (EI)
      1. 35.
      2. Gung-Yu Lin, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, “A Programmable Duty Cycle Corrector Based on Delta-Sigma Modulated PWM Mechanism,” IEEE Asia Pacific Conference on Circuits and Systems, Macao, pp.1406-1409, December 2008. (EI)
      1. 36.
      2. Kai Pong Wu, Ching-Yuan Yang, Jung-Mao Lin, “A 2.5Gb/s Oversampling Clock and Data Recovery Circuit with Frequency Calibration Technique,” IEEE Asia Pacific Conference on Circuits and Systems, Macao, pp.1356-1359, December 2008. (EI)
      1. 37.
      2. Chih-Hsiang Chang, Po-Vu Chen, Ching-Yuan Yang, “Doubled Sampling 100-MS/s 10-Bit Fully Differential Pipeline Analog to Digital Converter,” VLSI Design/CAD Symposium, Kenting, Taiwan, August 2008.
      1. 38.
      2. Chih-Hsiang Chang, Ching-Yuan Yang, “A Low-Voltage High-Frequency CMOS LC-VCO Using a Transformer Feedback,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Atlanta, pp.545-548, June 2008. (EI)
      1. 39.
      2. Soul-Yu Chao, Ching-Yuan Yang, “A 2.4-GHz 0.18-μm CMOS Doubly Balanced Mixer with High Linearity,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Taiwan, pp.247-250, April 2008. (EI)
      1. 40.
      2. Chih-Hsiang Chang, Chih-Yi Hsiao, Ching-Yuan Yang, “A 1-GS/s CMOS 6-bit Flash ADC with an Offset Calibrating Method,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Taiwan, pp.232-235, April 2008. (EI)
      1. 41.
      2. Meng-Ting Tsai, Ching-Yuan Yang, “A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-Mode WiFi/WiMAX Applications,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Morocco, pp.1384-1387, December 2007. (EI)
      1. 42.
      2. Tsung-Chan Wu, Ching-Yuan Yang, “A Transformer-Feedback Quadrature Voltage-Controlled Oscillator Using a Transconductance Tuning Technique,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Taiwan, pp.449-452, December 2007. (EI)
      1. 43.
      2. Jun-Hong Weng, Ching-Yuan Yang, “An Active Gm-C Filter Using a Linear Transconductance,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Taiwan, pp.909-912, December 2007. (EI)
      1. 44.
      2. Chih-Hsiang Chang, Ching-Yuan Yang, “A 0.18-um CMOS 16-GHz Varactorless LC-VCO with 1.2-GHz Tuning Range,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Korea, pp.107-110, November 2007. (EI)
      1. 45.
      2. Ping-Heng Wu, Ching-Yuan Yang, So-Yu Chao, “A Wide-Band PLL-Based Frequency Synthesizer with Adaptive Dynamics,” Proc. IEEE TENCON, Taipei, Taiwan, October 2007. (EI)
      1. 46.
      2. Kai-Pong Wu, Ching-Yuan Yang, Hsin-Ming Wu, Jung-Mao Lin, “A 3.125-Gb/s Burst-Mode Clock and Data Recovery Circuit With a Data-Injection Oscillator Using Half Rate Clock Techniques,” Proc. IEEE TENCON, Taipei, Taiwan, October 2007. (EI)
      1. 47.
      2. Jun-Hong Weng, Jing-Shing Wen, Chiing-Yuan Yang, “A High-Speed ROM-less Direct Digital Frequency Synthesizer Realized by a Segmented Non-linear DAC,” Proc. IEEE TENCON, Taipei, Taiwan, October 2007. (EI)
      1. 48.
      2. Chih-Hsiang Chang, Ching-Yuan Yang , “A 8-bit 150-MS/s Fully Differential Dual-channel Time-interleaved Pipeline A/D Converter,” Proc. 18th VLSI Design/CAD Symp., Taiwan, pp.363-366 , August 2007.
      1. 49.
      2. Hsin-Ming Wu, Ching-Yuan Yang, “A 3.125-GHz Limiting Amplifier for Optical Receiver System,” Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp.210-213, December 2006. (EI)
      1. 50.
      2. Chia-Chieh Tu, Ching-Yuan Yang, “A 6.5-GHz LC VCO with Integrated-Transformer Tuning,” Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp.511-514, December 2006. (EI)
      1. 51.
      2. Ming-Bin Chen, Ching-Yuan Yang, Meng-Ting Tsai, “A Fractional-N Frequency Synthesizer with a Ripple-Suppressed Loop Filter for IEEE 802.11a/b/g Channels,” Proc. 17th VLSI Design/CAD Symp., Taiwan, pp.113-116, August 2006.
      1. 52.
      2. Wen-Ger Wong, Chia-Chieh Tu, Ching-Yuan Yang, “A Spread-Spectrum Clock Generator Using Phase-Compensation Fractional PLL,” Proc. 17th VLSI Design/CAD Symp., Taiwan, pp.121-124, August 2006.
      1. 53.
      2. Ken-Hao Chang, Kai-Pong Wu, Ching-Yuan Yang, “A Half-Rate Clock and Data Recovery Circuit with a Phase-Realignment Oscillator,” Proc. 17th VLSI Design/CAD Symp., Taiwan, pp.129-132, August 2006.
      1. 54.
      2. Te-Ming Tseng, Hsin-Ming Wu, Ching-Yuan Yang, “A 3.125-Gb/s Laser Driver Using a Dual-Loop Control for Optical Transmitters,” Proc. 17th VLSI Design/CAD Symp., Taiwan, pp.645-648, August 2006.
      1. 55.
      2. Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, and Ching-Yuan Yang, “A 1.8-Gb/s Burst-Mode Clock and Data Recovery Circuit with a 1/4-Rate Clock Technique,” Proc. IEEE International Symposium on Circuits and Systems, pp.3073-3076, May 2006. (EI)
      1. 56.
      2. Meng-Ting Tsai and Ching-Yuan Yang, “A Frequency Synthesizer Realized by a Transformer-Based Voltage-Controlled Oscillator for IEEE 802.11a/b/g Channels,” Proc. IEEE International Symposium on Circuits and Systems, pp.5199-5202, May 2006. (EI)
      1. 57.
      2. Jun-Hong Weng, Chong-Jng Yu, Ching-Yuan Yang, and Peng-Chang Yang, “A Low-Noise Microsensor Amplifier with Automatic Gain Control System,” Proc. IEEE International Symposium on Circuits and Systems, pp.1410-1413, May 2006. (EI)
      1. 58.
      2. Ching-Yuan Yang, Ken-Hao Chang, Jung-Mao Lin, and Te-Ming Tseng, “A 12-MHz Voltage/Temperature Independent Frequency Generator,” VLSI/CAD symposium, Taiwan, August 2005.
      1. 59.
      2. Ching-Yuan Yang, Meng-Ting Tsai, Wen-Ger Wong, “A CMOS Continuous-Time Gm-C Low Pass Filter With On-Chip Automatic Tuning,” VLSI/CAD Symposium, Taiwan, August 2005.
      1. 60.
      2. Ching-Yuan Yang, Chih-Hsiang Chang,, “A Low-Power 8-bit 200-Ms/s Fully Differential CMOS Pipeline A/D Converter,” VLSI/CAD Symposium, Taiwan, August 2005.
      1. 61.
      2. Ching-Yuan Yang and Yu Lee, “A 0.18-um CMOS 1-Gb/s Serial Link Transceiver by Using PWM and PAM Techniques,” Proc. IEEE International Symposium on Circuits and Systems, pp.1150-1153, May 2005. (EI)
      1. 62.
      2. Ching-Yuan Yang, Jen-Wen Chen and Meng-Ting Tsai, “A High-Frequency Phase-Compensation Fraction-N Frequency Synthesizer,” Proc. IEEE International Symposium on Circuits and Systems, pp.5091-5094, May 2005. (EI)
      1. 63.
      2. Ching-Yuan Yang, Yu Lee and Cheng-Hsing Lee, “A 1.25Gb/s Half-Rate Clock and Data Recovery Circuit,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-DAT), pp.116-119, April 2005.
      1. 64.
      2. Ching-Yuan Yang, Jen-Wen Chen and Kuei-Zu Jiang, “A 1.6-GHz Delta-Sigma Modulated Fractional-N Frequency Synthesizer,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Taiwan, pp.157-160, April 2005. (EI)
      1. 65.
      2. Ching-Yuan Yang, Cheng-Hsing Lee and Yu Lee, “A 1.25Gb/S Clock and Data Recovery Circuit Using Half Rate Clock Technique,” Applied Science and Technology Conference (ASTC)- Photonics and Communications, December 2004.
      1. 66.
      2. Ching-Yuan Yang and Yu Lee, “A High Speed Serial Link Transceiver,” Applied Science and Technology Conference (ASTC)- Photonics and Communications, December 2004.
      1. 67.
      2. Ching-Yuan Yang and Tzu-Fan Chen, “A Dual-Band 2.4GHz/5.2GHz Fully Integrated CMOS Low Noise Amplifier,” Applied Science and Technology Conference (ASTC)- Photonics and Communications, December 2004.
      1. 68.
      2. Ching-Yuan Yang and Cheng-Hsing Lee, “A 1.25GB/S Clock and Data Recovery Circuit for Random Non-Return-to-Zero Data,” The 15th VLSI/CAD symposium, Taiwan, R.O.C., August 2004.
      1. 69.
      2. Ching-Yuan Yang and Kuei-Zu Jiang, “A Channel-Selecting Fractional-N Frequency Synthesizer for IEEE 802.11b Standard,” The 15th VLSI/CAD symposium, Taiwan, R.O.C., August 2004.
      1. 70.
      2. Chun-Chuan Liu, and Ching-Yuan Yang, “Analog Direct Synchronous Mirror Delay Circuit with Delay-Locked Loop for ASIC,” The 13th VLSI/CAD symposium, Taiwan, R.O.C., August 2002.
      1. 71.
      2. Yi-Zhen Huang, and Ching-Yuan Yang, “Dual-Loop Delay-Locked Loop for Duty-Cycle Adjustment,” The 13th VLSI/CAD symposium, Taiwan, R.O.C., August 2002.
      1. 72.
      2. Chia-Yang Chang, Po-Chang Chen, Ching-Yuan Yang, Yang-Han Lee, “The CMOS on-chip oscillator based on level tracking technique,” Proc. IEEE Asia-Pacific Conference on ASICs, pp.197 –200.
      1. 73.
      2. J. M. Hsu, Shen-Iuan Liu, Ching-Yuan Yang, and G. K. Dehng, “A 1 V CMOS Dynamic Back-Gate Forward Bias Prescaler for Frequency Synthesizer Application,” 1999 Analog VLSI Workshop, pp.45-50.
      1. 74.
      2. Ching-Yuan Yang, J. M. Hsu and Shen-Iuan Liu, “A 4-GHz CMOS Dual-Modulus Prescaler with High-Speed Dynamic Flip-Flops ,” The 9th VLSI/CAD symposium, Taiwan, R.O.C., pp.203-206, August 1998.
      1. 75.
      2. Ching-Yuan Yang, Wang-Chih and Shen-Iuan Liu, “Effectively Reduced Pull-in Time of PLL with Nonlinear Phase Comparator,” The 8th VLSI/CAD symposium, Taiwan, R.O.C., pp.205-208, August 1997.
      1. 76.
      2. Shen-Iuan Liu, Chih-Feng Lin, and Ching-Yuan Yang, “A PLL-Based Programmable Clock Generator with 15 to 180-MHz Lock Range,” The 7th VLSI/CAD symposium, Taiwan, R.O.C., pp.151-154, August 1996.
    3. C.專書
      1. 1.
      2. 劉深淵、楊清淵, “鎖相迴路,” 滄海書局, November 2006.
    4. E.專利
      1. 1.
      2. Chih-Hsiang Chang, Jung-Mao Lin, Ching-Yuan Yang, “Frequency Doubler,” United States Patent Application Publication, Pub. No: US 2011/0175651 A1, July 2011.
      1. 2.
      2. Chih-Hsiang Chang, Jung-Mao Lin, Ching-Yuan Yang, “Voltage Controlled Oscillator,” United States Patent Application Publication, Pub. No: US 2011/0018645 A1, January 2011.
      1. 3.
      2. Ching-Yuan Yang, Jung-Mao Lin, Yu-Min Lin, “Bust-Mode Clock And Data Recovery Circuit Using Phase Selecting Technology,” United States Patent Application Publication, Pub. No: US 2010/0040182 A1, February 2010.
      1. 4.
      2. Chia-Yang Chang, Po-Chang Chen, Yang-Han Lee, Ching-Yuan Yang, “Digital Adjustable Chip Oscillator,” US Patent No. 7002414 B2, February 2006.
      1. 5.
      2. 李其健、楊清淵、鄧光鎧、許峻銘、劉深淵, “快速動態式正反器,” 中華民國專利,發明第169564號,自民國90年2月21日起至民國100年10月28日止, .
      1. 6.
      2. 劉深淵、楊清淵, “利用單一導線補償時脈信號誤差之方法及電路,” 中華民國專利,發明第165962號,自民國91年10月21日起至民國110年1月11止, .
      1. 7.
      2. 張佳陽、陳柏璋、李揚漢、楊清淵, “數位可調式晶片振盪器,” 中華民國專利,發明第197975號,自民國93年2月21日起至民國111年11月7止, .
      1. 8.
      2. 楊清淵、劉深淵、陳良基, “高頻互補式金氧半雙模/多模前置分頻器,” 中華民國專利,發明第114359號,自民國89年4月11日起至民國105年9月22日止.
      1. 9.
      2. Ching-Yuan Yang, Shen-Iuan Liu and Liang-Gee Chen, “High-Frequency CMOS Dual/Multi-Modulus Prescaler,” US Patent No. 6094466, from Jul. 25, 2000 to Jan. 10, 2017.
      1. 10.
      2. 楊清淵、劉深淵, “除4/5電路,” 中華民國專利,發明第107136號,自民國88年8月21日起至民國106年10月1日止.
      1. 11.
      2. Ching-Yuan Yang, Shen-Iuan Liu, “Divide-by-4/5 counter,” US Patent No. 5930322, from Jul. 27, 1999 to Oct. 28, 2017.
 
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