Faculty SOC Group
  1. Faculty
 
  1. SOC Group
 
  1. Hwang, Yin-Tsung
  2.  
        1. Position
        2. Professor
        1. Education
        2. Ph.D. in Electrical Engineering, University of Wisconsin - Madison, USA
        1. Tel
        2. (04) 22851549 - 826
        1. Laboratory
        2. SOC & DSP Lab 717B
  3. Experiences
  4. Professor, Department of Electrical Engineering, National Chung Hsing University, 02/2014-present
    Director, Meng-Yao Chip Center, 08/2007-07/2010
    Associate Professor, Department of Electrical Engineering, National Chung Hsing University, 08/2005-01/2014
    Associate Professor, Department of Electronic Engineering, National Yunlin University of Science and Technology, 08/1993-07/2005
    Section Chief, Technology Service Section, Office of Technology Cooperation, National Yunlin University, 09/1997-01/2003
    Advisor, Scalable Video Codec Project, Electronics & Optoelectronics Research Laboratories, Industrial Technology Research Institute, 01/2003-03/2003
    Advisor, DAB Project, Information & Communications Research Laboratories, Industrial Technology Research Institute,08/1999-01/2000
    Engineer, Intel Inc. IMD dept., Folsom, CA. USA, 06/1992-09/1992
    Teaching Assistant, University of Wisconsin, Madison, U.S.A., 01/1990-05/1992
    Research Assistant, University of Wisconsin, Madison, U.S.A., 08/1984-06/1985
  5.  
  6. Research Areas
  7. Wireless/wired communication baseband IC design
    Video/Audio Codec SOC design
    Low power circuit designs
    Embedded systems and FPGA prototyping
  8.  
  9. Academic Service
  10. - 2014 ~ 2016, Taiwan Integrated Circuits Design Association, Council member
    - 2012 ~ 2013, IEEE Circuits & Systems Society, Taipei Chapter, executive secretary
    - 2012 IEEE Asia Pacific Conference on Circuits & Systems, Technical program chair
    - 2012 ~ now, IEEE CAS DiSP technical committee, TC member
    - 2012 IEEE International Conference on Circuits & Systems, International Liaison
    - 2011 ~ now, IEEE CAS, Nano-Giga technical committee, TC member
    - 2008 ~ 2012, International Symposium on VLSI Design, Automation & Test, TC member
    - 2007, High Performance Computing & Compiler Techniques Conference, technical program chair
    - 2004 ~ 2006, Taiwan Integrated Circuits Design Association, Council member
    - 2002 ~ 2006, Ministry of Education, Prototyping & Layout Alliance, chair
    - 2001 ~ now, VLSI/CAD Symposium, TPC member
    - 2001 ~ now, High Performance Computing & Compiler Techniques Conference, TPC member
    - 2000, VLSI/CAD Symposium, program chair
  11.  
  12. Awards
  13. Nothing
  14.  
  15. Selected Publications
    1. A.期刊論文
      1. 1.
      2. S.-M. Siao, M.-H. Sheu, Yin-Tsung Hwang, S.-Y. Wang, “Efficient reverse converter design for the new four-moduli set,” Journal of Chinese Institute of Engineers, no.3, pp.1-8, March 2017. (SCI、EI)
      1. 2.
      2. M.-H. Sheu, S.-M. Siao, Yin-Tsung Hwang, C.-C. Sun, Y.-P. Lin, “New adaptable three moduli set for residue number system based finite impulse response implementation,” IEICE Electronics Express, vol.13, no.11, pp.1-9, May 2016. (SCI、EI)
      1. 3.
      2. 3. M.-H. Sheu, S.-M. Siao, Yin-Tsung Hwang, Y.-C. Wang and K.-T. Lee, “New reverse converter design for 4-moduli set {2^2n,2^(n+1)-1, 2^n/2-1,2^n/2+1},” ICIC Express letter, Part B: applications, vol.7, no.5, pp.1111-1117, January 2016. (EI)
      1. 4.
      2. 6. M.-H. Sheu, S.-M. Siao, Y.-C. Kuo, Yin-Tsung Hwang, J.-J. Jhang, G.-Y. Lin, “New efficient reverse converter for 3 moduli set based on new CRT-I,” ICIC Express letter, Part B: applications, vol.6, no.2, pp.557-562, February 2015. (EI)
      1. 5.
      2. Jin-Fa Lin, Yin-Tsung Hwang, Chen-Syuan Wong and Ming-Hwa Sheu, “Single-ended structure sense-amplifier based flip-flop for low-power systems,” IET Electronics Letters, vol.51, no.1, pp.20-21, January 2015. (SCI、EI)
      1. 6.
      2. Jing-Shiun Lin, Yin-Tsung Hwang, Shih-Hao Fang, Po-Han Chu and Ming-Der Shieh, “Low-complexity High-throughput QR Decomposition Design for MIMO Systems,” IEEE Transactions on Very Large Scale Integration Systems, pp.accepted, January 2015. (SCI、EI)
      1. 7.
      2. Yin-Tsung Hwang, Ming-Wei Lyu, Chen-Cheng Lin, “A Low Complexity Embedded Compression Codec Design with Rate Control for High Definition Video,” IEEE Transcations on Circuits and Systems for Video Technology, accepted, (regular paper), December 2014. (SCI、EI)
      1. 8.
      2. Yin-Tsung Hwang, Wei-Da Chen and Cheng-Ru Hung, “A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High Throughput VLSI Implementation,” IEEE Transactions on Circuits and Systems I: Regular papers, vol.64, no.4, pp.1170 - 1182, April 2014. (SCI、EI)
      1. 9.
      2. Wei-Da Chen and Yin-Tsung Hwang, “A Constant Throughput Geometric Mean Decomposition Scheme Design for Wireless MIMO Precoding,” IEEE Transactions on Vehicular Technology, vol.62, no.5, May 2013. (SCI、EI)
      1. 10.
      2. Yin-Tsung Hwang and Jin-Fa Lin, “Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique,” IEEE Transactions on Very Large Scale Integration Systems, vol.20, no.9, September 2012. (SCI、EI)
      1. 11.
      2. Yin-Tsung Hwang and Wei-Da Chen, “Design and Implementation of a High Throughput Fully-Parallel Complex-Valued QR Factorization Chip,” IET Circuits, Devices & Systems, , vol.5, pp.424-432, May 2011. (SCI、EI)
      1. 12.
      2. Yin-Tsung Hwang, Jin-Fa Lin and Ming-Hwa Sheu, “Low Power Pulse-Triggered Flip-Flop Design with Conditional Pulse Enhancement Scheme,” IEEE Transactions on Very Large Scale Integration Systems, February 2011. (SCI、EI)
      1. 13.
      2. Yin-Tsung Hwang and Cheng-Chen Lin, “Lossless Hyperspectral Image Compression System Based on HW/SW Co-design,” IEEE Embedded System letters, January 2011.
      1. 14.
      2. Yin-Tsung Hwang, Feng-Ming Chang, Shin-Wen Chen, “Narrow Band Power Line Communication Transceiver Design for Household Control Systems,” Journal of Engineering, vol.22, no.1, pp.1-22, January 2011.
      1. 15.
      2. Chung-Chuan Wang, Yin-Tsung Hwang, Chin-Chen Chang and Jinn-Ke Jan, “Hiding Information in Binary Images with Complete Reversibility and High Embedding Capacity,” International Journal of Innovative Computing, Information and Control, vol.6, no.12, December 2010. (SCI、EI)
      1. 16.
      2. Cheng-Chen Lin and Yin-Tsung Hwang, “Lossless Compression of Hyperspectral Images Using Adaptive Prediction and Backward Search Schemes,” Journal of Information Science & Engineering, December 2010. (SCI、EI)
      1. 17.
      2. J.F. Lin, Yin-Tsung Hwang, M.H. Sheu, “A Low Complexity Dual-Mode Pulse-Triggered Flip- Flop Design Based on Unified AND/XNOR Logic,” IEICE Trans. on Fundamental, vol.Vol.E93-A, no.12, December 2010. (SCI、EI)
      1. 18.
      2. J.F. Lin, Y.T. Hwang, M.H. Sheu, “Low Power Pulse Generator Design Using Hybrid Logic,” IEICE Trans. on Fundamental, vol.E93-A, no.6, June 2010. (SCI、EI)
      1. 19.
      2. J.F. Lin, Y.T. Hwang, M.H. Sheu, “A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits,” IEICE Trans. on Fundamental, vol.Vol.E93-A, no.4, April 2010. (SCI、EI)
      1. 20.
      2. Cheng-Chen Lin and Yin-Tsung Hwang, “An Efficient Lossless Compression Scheme for Hyperspectral Images Using Two-Stage Prediction,” IEEE Transactions on Geographical Remote Sensing Letters, vol.7, no.3, pp.558-562, January 2010. (SCI、EI)
      1. 21.
      2. Y.T. Hwang and Wei-Da Chen, “A low complexity complex QR factorization design for real time MIMO signal detection,” International Journal of Electrical Engineering, vol.16, no.3, pp.185-194, March 2009. (EI)
      1. 22.
      2. J.F. Lin, Y.T. Hwang, M.H. Sheu, “Low complexity pulse generator designs,” IEICE Trans. on Fundamental, vol.E91-A, July 2008. (SCI、EI)
      1. 23.
      2. J.F. Lin, Y.T. Hwang, M.H. Sheu and C.C. Ho, “A Novel High Speed and Energy Efficient 10-Transistor Full Adder Design,” IEEE Transaction on Circuits & Systems I, vol.54, pp.1050-1059, May 2007. (SCI、EI)
      1. 24.
      2. C.H. Wu, C.M. Wu, M.D. Shieh, and Y.T. Hwang, “VLSI architectural design tradeoffs for sliding-window log-map decoders,” IEEE Trans. on VLSI systems. (SCI、EI)
      1. 25.
      2. T.Y. Hwang, C.T. King, Y.T. Hwang and Y.L. Lin, “embedded software consortium of Taiwan,” ACM Transactions in Embedded Computing Systems. (SCI、EI)
      1. 26.
      2. C.H. Wu, C.M. Wu, M.D. Shieh, and Y.T. Hwang, “High speed, low complexity systolic design of novel iterative division algorithms in GF(2^m),” IEEE Trans. on computers, vol.53, no.3, pp.375-380, March 2004. (SCI、EI)
      1. 27.
      2. M.-D. Shieh, C.-M. Wu, Y.-T. Hwang, H.-F. Lo, and M.-H. Hu, “Realization of Area-Efficient FFT Processors for DAB System,” Journal of the Chinese Institute of Electrical Engineering, vol.10, no.3, pp.269-280. (EI)
      1. 28.
      2. C.H. Wu, C.M. Wu, M.D. Shieh, and Y.T. Hwang, “Novel Algorithms and VLSI Design for Division over GF(2m),” IEICE Trans. on Fundamentals, vol.E85-A, no.5, pp.1129-39, May 2002. (SCI、EI)
      1. 29.
      2. Yin-Tsung Hwang, Ying-Chou Chung and Jer-Sho Hwang, “High Performance Code Generation for Digital Signal Processors,” Journal of Computers, vol.12, no.3, pp.50-62, September 2000.
      1. 30.
      2. Yin-Tsung Hwang, Yuan-Hung Wang and Jer-Sho Hwang, “Rapid Prototyping of Hardware/Software Codesign for Embedded Signal Processing,” Journal of Information Science & Engineering, vol.14, no.3, pp.605-632. (SCI、EI)
      1. 31.
      2. Yin-Tsung Hwang and Jer-Sho Hwang, “Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors,” Journal of Information Science & Engineering, vol.14, no.1, pp.138-165. (SCI、EI)
      1. 32.
      2. Yin-Tsung Hwang and Yu Hen Hu, “A Unified Partitioning and Scheduling Scheme for Mapping Multi-stage Regular Iterative Algorithms onto Systolic Arrays,” Journal of VLSI Signal Processing, vol.11, pp.133-150. (SCI、EI)
      1. 33.
      2. Yin-Tsung Hwang and Yu Hen Hu, “MSSM - A Design Aid for Multi-Stage Systolic Mapping,” Journal of VLSI Signal Processing, vol.4, pp.125-145. (SCI、EI)
    2. B.研討會論文
      1. 1.
      2. Yin-Tsung Hwang, Bing-Cheng Tsai, and others, “Feature Points Based Video Object Tracking for Dynamic Scenes and Its FPGA System Prototyping,” Yin-Tsung Hwang, Bing-Cheng Tsai, and others, “Feature Points Based Video Object Tracking for Dynamic Scenes and Its FPGA System Prototyping,” Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, KitaKyuShu, Japan, August 2014.
      1. 2.
      2. Yin-Tsung Hwang and Juin-Yen Chen, “An IP Interface Design Compiler with SystemC based Input Specifications,” IEEE NEWCAS 2014, Quebec, Canada, June 2014.
      1. 3.
      2. Yin-Tsung Hwang, Yi-Yo Chen, “Design and Implementation of a high throughput soft output MIMO signal detector,” IEEE workshop on Signal Processing Systems, September 2013.
      1. 4.
      2. Yin-Tsung Hwang, Yi-Yo Chen, Sung-Jun Tsai, “A 2G Samples/s Real-Valued FFT Processor Design and Its FPGA Realization for Optical OFDM Systems,” The 28th Int’l Technical Conference on Circuits/Systems, Computers and communications, YeoSu, Korea, July 2013.
      1. 5.
      2. Yin-Tsung Hwang, Yi-Chih Chen, Cheng-Ru Hong, and others, “Design and implementation of an FMCW radar baseband processor,” IEEE Asia Pacific Caircuits and Systems Conference, December 2012.
      1. 6.
      2. Jing-Shiun Lin, Yin-Tsung Hwang, Po-Han Chu, Ming-Der Shieh, and Shih-Hao Fang, “An Efficient QR Decomposition Design for MIMO Systems,” IEEE ISCAS 2012, Seoul, Korea, May 2012.
      1. 7.
      2. Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, “Low Power 10-Transistor Full Adder Design Based on Degenerate Pass Transistor Logic,” IEEE ISCAS 2012, Seoul, Korea, May 2012.
      1. 8.
      2. Yin-Tsung Hwang and Tao-Hsing Huang, “Efficient TWIN-VQ Audio Decoder Implementation on a Configurable Processor using Instruction Extension,” IEEE ISCAS 2012, Seoul, Korea, May 2012.
      1. 9.
      2. Yin-Tsung Hwang, Sung-Jun Tsai, Yi-Yo Chen, “Design and Implementation of an optical OFDM baseband receiver in FPGA,” VLSI-DAT Symposium, Hsinchu, April 2012.
      1. 10.
      2. 9. Jiun-Yan Chen, Kuo-Feng Hung, Hsin-Yi Lin, Yen-Chung Chang, Yin-Tsung Hwang, Ciao-Kai Yu, Cheng-Ru Hong, Chin-Chia Wu, Yung-Jung Chang, “Real-time FPGA-based Template Matching Module for Visual Inspection Application,” The 2012 IEEE/ASME International Conference on Advanced Intelligent Mechatronics, March 2012.
      1. 11.
      2. Yin-Tsung Hwang and Shin-Wen Chen, “Hardware Efficient Design for Narrow Band Power Line Communication Modem,” IEEE TENCON, Bali, Indonesia, November 2011.
      1. 12.
      2. Yin-Tsung Hwang, Feng-Ming Chang, and Shin-Wen Chen, “Low Complexity Baseband Transceiver Design for Narrow Band Power Line Communication,” IEEE ISCAS 2011, Barzil, May 2011.
      1. 13.
      2. Cheng-Ru Hong , Yin-Tsung Hwang, Wei-Chieh Hsu, Chi-Ho Chang, Jui-Chi Huang, Ho-En Liao, “Programmable AND-CFAR Signal Detector Design and Its FPGA Prototyping for FMCW Radar Systems,” VLSI-DAT Symposium, April 2011.
      1. 14.
      2. Yin-Tsung Hwang, Chen-Cheng Lin, Ming-Wei Lyu, “Design and Implementation of a Low Complexity Lossless Video Codec,” IEEE Asia Pacific Conference on Circuits & Systems, Malaysia, October 2010.
      1. 15.
      2. Cheng-Chen Lin, Yin-Tsung Hwang, Yi-Chen Chang, Jiun-Jiang Chen, and Ming-Wei Liu, “Lossless Coding of Multiband Images Using Interband Data Correlation and Error Feedback Prediction Scheme,” 6th international conf. on intelligent information hiding and Multimedia Signal Processing, Darmstadt, Germany, August 2010.
      1. 16.
      2. Cheng-Chen Lin, Yin-Tsung Hwang, Yi-Chen Chang, and Ming-Wei Liu, “Efficient Lossless Data Compression Codec Design for Multiband Images,” 21st VLSI/CAD design symposium, August 2010.
      1. 17.
      2. Cheng-Chen Lin, Yin-Tsung Hwang, Yi-Chen Chang, and Ming-Wei Liu, “High efficiency and low complexity lossless image compression system,” 21st VLSI/CAD design symposium, August 2010.
      1. 18.
      2. Yin-Tsung Hwang and Wei-Da Chen, “MMSE-QR Factorization Systolic Array Design for Applications in MIMO Signal Detections,” IEEE ISCAS, Paris, France, May 2010.
      1. 19.
      2. Yin-Tsung Hwang, Feng-Ming Chang, and Shin-Wen Chen, “Power Line Communication Baseband Processor Design for Smart Power Control Network,” International Conference on High-Speed Circuits Design, 2010, April 2010.
      1. 20.
      2. Yin-Tsung Hwang and Hwa-Hsin Luo, “Automatic IP Interface Synthesis Supporting Multi-Layer Communication Protocols in SoC Designs,” The Fifth International Conference on Information Assurance and Security, XiAn, China, August 2009.
      1. 21.
      2. Yin-Tsung Hwang, Wei-Da Chen, “Systolic MMSE-QR Factorization Design Based on a Symmetrical Nullification Scheme,” 20th VLSI/CAD design symposium, Hualien, Taiwan, August 2009.
      1. 22.
      2. Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu and Yu-Ru Cho, “A Novel Low Power Pulse-Triggered Flip-Flop Design with Pulse Width Control Scheme,” 20th VLSI/CAD design symposium, Hualien, Taiwan, August 2009.
      1. 23.
      2. Yin-Tsung Hwang, Cheng-Chen Lin, Ruei-Ting Hung1, Jiun-Jiang Chen, “Lossless Hyperspectral Image Compression System based on HW/SW Co-design,” Conference on Innovative Application of System Prototyping and Circuit Design, June 2009.
      1. 24.
      2. Yin-Tsung Hwang, Jun-Yen Chen and Jun-Jieh Chiu, “HW/SW Auto-Coupling for fast IP Integration in SoC Designs,” IEEE ICESS, Chen-Du, China, July 2008.
      1. 25.
      2. Yin-Tsung Hwang, Wei-Da Chen, “A Low Complexity Complex QR Factorization Design for Signal Detection in MIMO OFDM Systems,” IEEE ISCAS, Seattle, USA, May 2008.
      1. 26.
      2. 2Jun-Yen Chen, Yin-Tsung Hwang, Jun-Jieh Chiu, “An IP Interface Compiler with SystemC Protocol Specifications,” Workshop on Compiler techniques and high performance computing, Taipei, February 2008.
      1. 27.
      2. Yin-Tsung Hwang, Cheng-Chen Lin and Kuan-Hsun Tseng, “Scalable Lossless Video Coding Based on Adaptive Motion Compensated Temporal Filtering,” IEEE Int’l Symp. on Multimedia, Workshop on Scalable Video Coding & Transport, December 2007.
      1. 28.
      2. Yin-Tsung Hwang, Ying-Ji Chen and Wei-Da Chen, “Scalable FFT Kernel Designs for MIMO OFDM Based Communication Systems,” IEEE TENCON, October 2007.
      1. 29.
      2. Cheng-Chen Lin, Yin-Tsung Hwang, Kwan-Hsun Tseng, Shao-Wen Chen, “wavelet based lossless video compression using motion compensated temporal filtering,” IEEE workshop on Signal Processing Systems, ShanHai, China, October 2007.
      1. 30.
      2. Yin-Tsung Hwang1, Jin-Fa Lin, Ming-Hwa Sheu and Chia-Jen Sheu, “low power multipliers using enhanced row bypassing schemes,” IEEE workshop on Signal Processing Systems, ShangHai, China, October 2007.
      1. 31.
      2. Jin-Fa Lin *2, Yin-Tsung Hwang #1, Ming-Hwa Sheu * and Wei-Rong Ciou, “A Novel Low Complexity Pulse-Triggered Flip-Flop Design with Dual Triggering Mode,” 18th VLSI/CAD design symposium, August 2007.
      1. 32.
      2. Y.T. Hwang, J.F. Lin, M.H. Sheu and C.J. Sheu, “Low Power Multiplier Designs Based on Improved Column Bypassing Schemes,” IEEE APCCAS’06, Singapore, December 2006.
      1. 33.
      2. Yin-Tsung Hwang, Tao-Hsin Huang, “Efficient Implementation of an MPEG 4 TWIN-VQ Audio Decoder on a Configurable Processor with Instruction Extension,” Workshop on Compiler Techniques for High Performance Computing, October 2006.
      1. 34.
      2. Y.T. Hwang, J.Y. Chen and M.H. Sheu, “Automatic Generation of Programmable Parallel CRC & Scrambler Designs,” IEEE Workshop on SiPS 2006, Banff, Canada, October 2006.
      1. 35.
      2. Yin-Tsung Hwang, Sheng-Chi Peng and Jenn Kaie Lain, “A Low-Complexity Channel Estimator for MIMO-OFDM Systems,” IEEE ICCCAS, GuiLin, China, June 2006.
      1. 36.
      2. Jin-Fa Lin, Ming-Hwa Sheu and Yin-Tsung Hwang, “Low-Power and Low-Complexity Full Adder Designs for Wireless Base Band Applications,” IEEE ICCCAS, 2006, GuiLin, China, June 2006.
      1. 37.
      2. Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu and Cheng-Che Ho, “A High Speed and Energy Efficient Full Adder Design Using Complementary & Level Restoring Carry Logic,” IEEE ISCAS, Kose, Greece, May 2006.
      1. 38.
      2. Yin-Tsung Hwang, Sin-Chi Lai, “A novel MDCT/IMDCT computing kernel design,” IEEE ISCAS’05, AThen, Greece, October 2005.
      1. 39.
      2. Yin-Tsung Hwang, Chen-Yu Tsai and Cheng-Chen Lin, “Block-wise Adaptive Modulation for OFDM WLAN Systems,” IEEE ISCAS’05, Kobe, Japan, May 2005.
    3. E.專利
      1. 1.
      2. 黃穎聰等, “無失真視訊壓縮系統之動態補償時間濾波器之方法,” 中華民國專利,已核准, April 2014.
      1. 2.
      2. 黃穎聰等, “雙觸發邏輯電路,” 中華民國專利,已核准, August 2013.
      1. 3.
      2. 黃穎聰等, “以離散小波轉換處理影像之系統,” 中華民國專利,發明第I318073號, August 2009.
      1. 4.
      2. 黃穎聰等, “適用於小波轉換視訊編碼之低複雜度頻域移動估測方法,” 中華民國專利,發明第I 351882號, May 2009.
      1. 5.
      2. 黃穎聰等, “快速傅立葉轉換系統,” 中華民國專利,發明第I313825號, January 2009.
      1. 6.
      2. 黃穎聰等, “互補式進位邏輯電壓補償之全加器,” 中華民國專利,發明第I317903號, April 2008.
      1. 7.
      2. 黃穎聰等, “可規劃平行循環冗餘檢查電路及攪散器電路,” 中華民國專利,發明第I 327704號, January 2008.
      1. 8.
      2. Yin-Tsung Hwang and others, “Double-Triggered Logic Circuit,” 美國專利,patent no. US 7714627 B1, January 2006.
      1. 9.
      2. Yin-Tsung Hwang and others, “Full adder of complementary carry logic voltage compensation,” 美國專利,patent no. US 7508233 B2, January 2006.
      1. 10.
      2. Yin-Tsung Hwang and others, “Methods for encoding images according to object shapes,” 美國專利,patent no. US 7565023 B2, August 2005.
      1. 11.
      2. 黃穎聰等, “依據物件形狀進行影像編碼的處理方式,” 中華民國專利,發明第I 263172號, January 2005.
 
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