Faculty SOC Group
  1. Faculty
 
  1. SOC Group
 
  1. Yeong-Kang Lai
  2.  
        1. Position
        2. Professor & Chair
        1. Education
        2. Ph.D. in Electrical Engineering, National Taiwan U
        1. Tel
        2. 8864-22840688-827
        1. Laboratory
        2. Multimedia & Communication IC design Lab 611B
  3. Experiences
  4. Associate Professor r, Department of Electrical Engineering, National Chung Hsing University, 02/2003-present
    Assistant Professor, Department of Electrical Engineering, National Chung Hsing University, 08/2001-01/2003
    Assistant Professor, Department of Computer Science and Information Engineering, National Dong Hwa University, 08/1998-07/2001
    Assistant Professor, Department of Electronic Engineering, Chang Gung University, 08/1997-07/1998
  5.  
  6. Research Areas
  7. VLSI Design for Multimedia
    VLSI Design for Signal Processing
    VLSI Design for Data Security
    Video/Image Compression Technology
  8.  
  9. Academic Service
  10. 1. Associate Editor, IEEE Transactions on Consumer Electronics (SCI)
    2. Associate Editor, Journal of Circuits, Systems and Signal Processing (SCI)
    3. Lead Guest Editor, VLSI Design Journal
    4. Track Chair, 2014 IEEE International Conference on Consumer Electronics
    5. Technical Program Chair, Asia/Pacific Region, 2014 IEEE International Conference on Consumer Electronics
    6. Technical Program Committee Member, 2013 IEEE International Symposium on Consumer Electronics
    7. Technical Program Committee Member, 2013 IEEE Global Conference on Consumer Electronics
    8. Technical Program Chair, Asia/Pacific Region, 2013 IEEE International Conference on Consumer Electronics
    9. Technical Program Committee Member, 2012 IEEE Global Conference on Consumer Electronics
    10. Technical Program Committee Member, 2012 IEEE International Conference on Consumer Electronics
    11. Session Chair, 2011 IEEE International Symposium on Consumer Electronics
    12. Technical Program Committee Member, 2012 International Symposium on Electronic System Design, Kochi, India
    13. Technical Program Committee Chair, 2011 Very Large Scale Integrated Circuits and Computer Aided Design Symposium, Taiwan.
    14. Invited Session Organizer and Session Chair, 2010 International SoC Design Conference, Korea.
    15. Technical Program Committee Member, 2004 IEEE Asia Pacific Conference on Circuits and Systems, Taiwan.
  11.  
  12. Awards
  13. Nothing
  14.  
  15. Selected Publications
    1. A.期刊論文
      1. 1.
      2. Y.-L. Lai, C.-L. Chen, C.-H. Chang, C.-Y. Hsu, Y.-K. Lai, K.-K. Tseng, C.-C. Chen, and C.-Y. Zheng, “An intelligent health monitoring system using radio-frequency identification technology,” Technology and Health Care, vol.24, no.s1, pp.S421–S431, January 2016. (SCI)
      1. 2.
      2. C.-Y. Hsu, Y.-L. Lai, C.-C. Chen, Y.-T. Lee, K.-K. Tseng, Y.-K. Lai, C.-Y. Zheng, and H.-C. Jheng, “Time sequence image analysis of positron emission tomography using wavelet transformation,” Technology and Health Care, vol.24, no.s1, pp.S393–S400, January 2016. (SCI)
      1. 3.
      2. Y. K. Lai and Y. C. Chung,, “An efficient rasterization unit with ladder start tile traversal in 3D graphics systems,” accepted to be published in IEEE Trans. on Magnetics, vol.50, no.7, July 2014. (SCI、EI)
      1. 4.
      2. Y. K. Lai and Y. C. Chung, “3-D graphics processor unit with cost-effective rasterization using valid screen space region,” IEEE Trans. on Consumer Electronics, vol.59, no.3, pp.705-713, August 2013. (SCI、EI)
      1. 5.
      2. Y. K. Lai and S. M. Lee, “Wide color-gamut improvement with skin protection using content-based analysis for display systems,” IEEE/OSA J. Display Technol., vol.9, no.3, pp.146-153, March 2013. (SCI、EI)
      1. 6.
      2. Y. K. Lai, Y. F. Lai, and Y. C. Chen, “An effective hybrid depth-generation algorithm for 2D-to-3D conversion in 3D displays,” IEEE/OSA J. Display Technol., vol.9, no.3, pp.154-161, March 2013. (SCI、EI)
      1. 7.
      2. Y. K. Lai and Y. F. Lai, “Quality enhancement for scalable view window in touchable display systems,” IEEE/OSA J. Display Technol, vol.7, no.10, pp.537-543, October 2011. (SCI、EI)
      1. 8.
      2. Y. K. Lai, Y. F. Lai, and P. Y. Chen, “Content-Based LCD Backlight Power Reduction with Image Contrast Enhancement Using Histogram Analysis,” IEEE/OSA J. Display Technol, vol.7, no.10, pp.550-555, October 2011. (SCI、EI)
      1. 9.
      2. Y. K. Lai, L. F. Chen, and W. C. Chiou, “A Memory Interleaving and Interlacing Architecture for Deblocking Filter in H.264/AVC,” IEEE Trans. on Consumer Electronics, November 2010. (SCI、EI)
      1. 10.
      2. Y. K. Lai, L. F. Chen, and S. Y. Huang, “Parallel Motion Estimation Architecture Based on Fast Top-Winners Search Algorithm,” IEEE Trans. on Consumer Electronics, vol.56, no.3, pp.1837-1842, August 2010. (SCI、EI)
      1. 11.
      2. Y. K. Lai, and Y. F. Lai, “A Reconfigurable IDCT Architecture for Universal Video Decoders,” IEEE Trans. on Consumer Electronics, vol.56, no.3, pp.1872-1879, August 2010. (SCI、EI)
      1. 12.
      2. Y. K. Lai, L. F. Chen, “A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform,” IEEE Trans. on Consumer Electronics, vol.55, no.2, pp.400-407, May 2009. (SCI、EI)
      1. 13.
      2. Y. K. Lai and L. F. Chen, “A defect-tolerant reconfigurable nanoarchitecture design for multimedia applications,” Colloids and Surfaces A: Physicochem. Eng. Aspects, vol.313-314, pp.465-468, February 2008. (SCI、EI)
      1. 14.
      2. Y. K. Lai, Tian-En Hsieh, and L. F. Chen, “Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications,” Japanese Journal of Applied Physics, vol.46, no.4B, pp.2238-2243, April 2007. (SCI、EI)
      1. 15.
      2. Y. K. Lai, L. F. Chen, and C. W. Chiu, “A cost effective interconnection network for reconfigurable computing processor in digital signal processing,” IEICE Trans. on Electronics, vol.e89-c, no.11, pp.1674-1675, November 2006. (SCI、EI)
      1. 16.
      2. Y. K. Lai, L. F. Chen, and J. C. Chen, “A reconfigurable computing processor core for multimedia system-on-chip applications,” Japanese Journal of Applied Physics, vol.45, no.4B, pp.3336-3342, April 2006. (SCI、EI)
      1. 17.
      2. Y. K. Lai and L. F. Chen, “High-throughput configurable motion estimation processor core for video applicaitons,” Japanese Journal of Applied Physics, vol.45, no.4B, pp.3330-3335, April 2006. (SCI、EI)
      1. 18.
      2. Y. K. Lai, “A memory efficient motion estimator for three step search block-matching algorithm,” IEEE Trans. on Consumer Electronics, vol.47, no.3, pp.644-651, August 2001. (SCI、EI)
      1. 19.
      2. Y. K. Lai, Y. L. Lai, Y. C. Liu, P. C. Wu, and L. G. Chen, “VLSI implementation of the motion estimator with two-dimensional data-reuse,” IEEE Trans. on Consumer Electronics, vol.44, no.3, pp.623-629, August 1998. (SCI、EI)
      1. 20.
      2. Y. C. Liu, Y. K. Lai, T. H.Tsai, P. C. Wu, and L. G. Chen, “VLSI implementation of visual block pattern truncation coding,” IEEE Trans. on Consumer Electronics, vol.44, no.3, pp.490-499, August 1998. (SCI、EI)
      1. 21.
      2. Y. K. Lai and L. G. Chen, “A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm,” IEEE Trans. on Circuits and Systems for Video Technology, vol.8, no.2, April 1998. (SCI、EI)
      1. 22.
      2. P. C. Wu, L. G. Chen, and, Y. K. Lai , “A block shifting method for reduction of blocking effects in subband/wavelet image coding,” IEEE Trans. on Consumer Electronics, vol.44, no.1, pp.170-177, February 1998. (SCI、EI)
      1. 23.
      2. Y. L. Lai, Y. K. Lai, C. Y. Chang, and E. Y. Chang, “A novel fabrication technology of T-shaped-gate using EGMEA and PMIPK resists and E-Beam lithography,” Microelectronic Engineering, vol.41/42, pp.555-558, January 1998. (SCI、EI)
      1. 24.
      2. Y. K. Lai, L. G. Chen, H. T. Chen, M. J. Chen, Y. P. Lee, and P. C. Wu, “A novel video signal processor with programmable data arrangement and efficient memory configuration,” IEEE Trans. on Consumer Electronics, vol.42, no.3, pp.526-534, August 1996. (SCI、EI)
      1. 25.
      2. H. T. Chen, P. C. Wu, Y. K. Lai, and L. G. Chen, “A multimedia video conference system: using region base hybrid coding,” IEEE Trans. on Consumer Electronics, vol.42, no.3, pp.781-786, August 1996. (SCI、EI)
    2. B.研討會論文
      1. 1.
      2. Y.-F. Lai and Y.-K. Lai, “Design and Implementation of Reconfigurable IDCT Architecture for Multi-Standard Video Decoders,” Proc. of Int’l. SOC Conference (ISOCC)(Best Paper Award), Incheon, Korea, November 2010.
      1. 2.
      2. [2] L.-F. Chen, S.-Y. Huang, C.-Y. Liao, and Y.-K. Lai, “Hardware Efficient Coarse-to-Fine Fast Algorithm for H.264/AVC Variable Block Size Motion Estimation,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, ROC, May 2009.
      1. 3.
      2. L.-F. Chen, S.-P. Yang, and Y.-K. Lai, “Model-based Early Termination Scheme for H.264/AVC Inter Prediction,” Proc. of IEEE Int’l. Conference on Acoustics, Speech, and Signal Processing (ICASSP), Taipei, Taiwan, ROC, April 2009.
      1. 4.
      2. Y. K. Lai, L. F. Chen, T. E. Hsieh, and S. Y. Huang, “Hybrid parallel motion estimation architecture based on fast pel-subsampling algorithm,” Proc. of IEEE Int’l. Conference on Multimedia & Expo. (Student Best Paper Award), Germany, June 2008.
      1. 5.
      2. L. F. Chen, K. H. Li, C. Y. Huang, and, Y. K. Lai, “Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder,” Proc. of IEEE Int’l. Conference on Multimedia & Expo., Germany, June 2008.
      1. 6.
      2. Y. K. Lai, C. C. Chou, and Y. C. Chung, “A High-Speed 2-D Transform Architecture with Unique Kernel for Multi-Standard Video Applications,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), Seatle, USA, May 2008.
      1. 7.
      2. Y. K. Lai, C. C. Chou, and Y. C. Chung, “A Simple and Cost Effective Video Encoder with Memory-Reducing CAVLC,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), May 2005.
      1. 8.
      2. L. F. Chen, T. L. Huang and, Y. K. L, “Memory Analysis AND Architecture Enhancements for Low Cost and High Throughput Bit-Plane Coder in JPEG2000 Applications,” Proc. of IEEE Int’l. Conference on Acoustics, Speech, and Signal Processing, March 2005.
      1. 9.
      2. Y. K. Lai, Adik Liu, and L. F. Chen, “Fast and High-Accuracy Design and Implementation for Home Electronic Weighing Scale Applications,” Proc. of IEEE Int’l. Conference on Consumer Electronics, January 2005.
      1. 10.
      2. Y. K. Lai, L. F. Chen, and, T. L. Huang, “A High Throughput and Memory Efficient EBCOT Architecture for JPEG2000 in Digital Camera Applications ,” Proc. of IEEE Int’l. Conference on Consumer Electronics, January 2005.
      1. 11.
      2. Y. K. Lai and L. C. Chang, “A novel memoryless AES cipher architecture for networking applications,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), May 2004.
      1. 12.
      2. L. F. Chen and Y. K. Lai, “VLSI architecture of the reconfigurable computing engine for digital signal processing applications,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), May 2004.
      1. 13.
      2. Y. K. Lai and H. J. Hsu, “A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), May 2003.
      1. 14.
      2. Y. K. Lai and L. F. Chen, “A high data-reuse architecture with two-slice processing for full-search block-matching algorithm,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), May 2003.
      1. 15.
      2. L. F. Chen, H. J. Hsu, and Y. K. Lai, “A flexible and memory efficient motion estimator with parameters with parameters for MPEG applications,” Proc. of IEEE Int’l. Symposium on Intelligent Signal Processing and Communication systems, November 2002.
      1. 16.
      2. Y. K. Lai and L. G. Chen, J. Y. Lai, and T. M. Parng, “VLSI Architecture Design and Implementation for Twofish Block Cipher,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), pp.356 –359, May 2002.
      1. 17.
      2. Y. K. Lai and Y. C. Shu, “VLSI Architecture Design and Implementation for Blowfish Block Cipher with Secure Modes of Operation,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), pp.57-60, May 2001.
      1. 18.
      2. H. H. Hsieh and Y. K. Lai, “A Novel Fast Motion Estimation Algorithm Using Fixed Subsampling Pattern and Multiple Local Winners Search,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), pp.241 –244, May 2001.
      1. 19.
      2. Y. K. Lai, K. C. Chen, “A Novel VLSI Architecture for Lempel-Ziv-Based Data Compression,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), pp.617 –620, May 2000.
      1. 20.
      2. Y. K. Lai and Y. C. Shu, “A novel VLSI architecture for a variable-length key, 64-bit blowfish block cipher,” Proc. of IEEE Int’l. Workshop on Signal Processing System Design and Implementation (SiPS).
      1. 21.
      2. P. C. Wu, L. G. Chen, Y. C. Liu, and Y. K. Lai, “High Performance Architecture Design for Subband Synthesis Filter Banks,” in Proc. 1998 IEEE International Symposium on Consumer Electronics, Taipei, Taiwan, pp.WAB1-05-WAB1-09, October 1998.
      1. 22.
      2. Y. K. Lai, Y. L. Lai, Y. C. Liu, P. C. Wu, and L. G. Chen, “VLSI Implementation of the Motion Estimator with Two-Dimensional Data-Reuse,” Proc. of IEEE Int’l. Conference on Consumer Electronics, June 1998.
      1. 23.
      2. Y. K. Lai, G. S. Lin, C. W. Ku, and L. G. Chen, “A Novel VLSI Architecture of Motion Estimator for H.263 Video Coding,” Proc. of International Symposium on Multimedia Information Processing, December 1997.
      1. 24.
      2. Y. K. Lai, L. G. Chen, and M. C. Chiang, “A novel scalable architecture with memory interleaving organization for full search block-matching algorithm,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), pp.1229-1232.
      1. 25.
      2. P. C Wu, L. G. Chen, Y. C. Liu and Y. K. Lai , “Hardware efficient design of filter banks for video coding,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), pp.1213-1216.
      1. 26.
      2. T. H. Tsai, L. G. Chen, Y. C. Liu, Y. K. Lai and P. C Wu, “A novel MPEG-2 audio decoder with efficient data arrangement and memory configuration,” Proc. of IEEE Int’l. Conference on Consumer Electronics.
      1. 27.
      2. Y. C. Liu, L. G. Chen, P. C. Wu, Y. K. Lai, T. H. Tsai, and Y. P. Lee, “A true color video signal processing system and its real-time chip implementation,” Proc. of IEEE Int. Conference on Consumer Electronics.
      1. 28.
      2. Y. K. Lai, L. G. Chen, and Y. P. Lee, “A Flexible Data-Interlacing Architecture for Full-Search Block-Matching Algorithm,” Proc. of IEEE Int. Conference on Application-specific Systems, Architectures and Processors.
      1. 29.
      2. Y. K. Lai, L. G. Chen, and M. C. Chiang, “An efficient array architecture with data-rings for 3-step hierarchical search block matching algorithm,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS).
      1. 30.
      2. Y. K. Lai, L. G. Chen, P. C Wu, and T. H. Tsai, “A flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation,” Proc. of IEEE Int’l. Conference on Image Processing.
      1. 31.
      2. Y. K. Lai, L. G. Chen, and M. C. Chiang, “A novel video signal processor with reconfigurable pipelined architecture,” Proc. of IEEE Int’l. Symposium on Circuits and Systems (ISCAS), pp.73-76.
      1. 32.
      2. Y. K. Lai and L. G. Chen, “A novel video signal processor with programmable data arrangement and efficient memory configuration,” Proc. of IEEE Int’l. Conference on Consumer Electronics, pp.182-183.
      1. 33.
      2. P. C. Wu, L. G. Chen, Y. K. Lai, and T. H. Tsai, “Design strategy for three-dimensional subband filter banks,” Proc. of IEEE Int’l. Conference on Image Processing, pp.605 –608.
      1. 34.
      2. P. C. Wu, L. G. Chen, Y. C. Liu, and Y. K. Lai, “Investigation of filtering permutation schemes in three-dimensional subband filter banks,” Proc. of IEEE Int’l. Workshop on Intelligent Signal Processing and Communication Systems.
    3. D.技術報告
      1. 1.
      2. 賴永康, “105-2221-E-005-081,” 基於物聯網的智慧社區感知技術:安全監控與隱私感知:應用於智慧社區之即時環景監控立體視訊編解碼器, January 2017.
      1. 2.
      2. 賴永康, “103-2220-E-005-008,” 用於個人安全、資訊安全、娛樂之低功耗智慧型穿戴式裝置系統:智慧型穿戴式裝置之超低功率立體視覺處理器設計, October 2016.
      1. 3.
      2. 賴永康, “102-2220-E-005-004,” 智慧行車安全監控嵌入式系統設計:應用於汽車安全監控之感知3D視訊編解碼器, April 2015.
    4. E.專利
      1. 1.
      2. 賴永康, “萬用矩陣乘法方法、電路及其應用,” 中華民國發明專利, February 2014.
      1. 2.
      2. 賴永康, “高解析度高頻之影像處理晶片的驗證系統,” 中華民國發明專利:專利權號數號:發明第418816號, December 2013.
      1. 3.
      2. 賴永康, “Architecture for performing two-dimensional discrete wavelet transform,” 美國發明專利: 專利號碼:6,587,589, July 2003.
      1. 4.
      2. 賴永康, “適用於執行二維離散波元轉換之架構,” 中華民國發明專利:專利權號數號:發明第160548號,專利期限:91.08.01~109.02.02.
      1. 5.
      2. 賴永康, “Motion Estimator Employing a Three-Step Hierarchical Search Block Matching Algorithm ,” 美國發明專利, 專利號碼:6,160,850, December 2000.
      1. 6.
      2. 賴永康, “Array Architecture with Data-Rings for 3-Step Hierarchical Search Block Matching Algorithm,” 美國發明專利, 專利號碼:6,118,901, September 2000.
      1. 7.
      2. 賴永康, “應用三步驟階層式搜尋區塊比對法之移動估測器,” 中華民國發明專利:專利權號數號:發明第110352號。.
      1. 8.
      2. 賴永康, “針對三步驟階搜尋區塊比對演算法之資料環陣列架構,” 中華民國發明專利:專利權號數號:發明第102678號。.
 
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