Faculty SOC Group
  1. Faculty
 
  1. SOC Group
 
  1. Robert Chen-Hao Chang
  2.  
        1. Position
        2. Distinguished Professor
        1. Education
        2. Ph.D. in EE, University of Southern California
        1. Tel
        2. 886-4-22851549-263
  3. Experiences
  4. *Dean, College of Science and Technology, National Chi Nan University, Nantou, Taiwan, 2014/8~present
    *Deputy Director General - National Chip Implementation Center, NARLabs, Hsinchu, Taiwan (2011/3~2014/1)
    *Distinguished Professor (2012/2~present), Professor (2003/8~2012/1), Assoc. Professor (1996/8~2003/7) - Dept. of Electrical Engineering, National Chung Hsing Univ., Taichung, Taiwan
    *Chapter Chair - IEEE Circuits and Systems Society Taipei Chapter (2011/1~ 2012/12)
    *Chairman - Dept. of Electrical Engineering, National Chung Hsing Univ. (2006/8~2008/7)
    *Director - Center for Research and Development of Engineering Technology, School of Engineering, National Chung Hsing University, Taichung, Taiwan (2005/8~2006/7)
    *Director - Meng Yao Chip Center, Dept. of EE, National Chung Hsing Univ. (2000/12~2004/7)
  5.  
  6. Research Areas
  7. Mixed-Signal IC Design
    SoC & Signal Processing Systems
  8.  
  9. Academic Service
  10. *Chapter Chair
     Chair, IEEE Circuits and Systems Society Taipei Chapter, 2011~2012
    *Editor for Journals
     Assoc. Editor, IEEE Trans. on VLSI Systems, 2010 ~ 2014
     Assoc. Editor, IEEE Circuits and Devices Magazine, 2004
     Editor, Journal of Engineering, National Chung Hsing University, 2003~2010
    *Member of technical committees
     VLSI Systems & Applications Technical Committee, IEEE Circuits and Systems Society, 2004~present
     Nanoelectronics and Gigascale Systems Technical Committee, IEEE Circuits and Systems Society, 2009~present (Chair-elect 2013/7~2015/6, Secetary 2011/7~2013/6)
    *Conference organizer or session chair
    -International:
     Tutorial Co-chair, IEEE BioCAS, 2012
     Technical Program Committee Member, IEEE Asian Solid-State Circuits Conference, 2011~2013
     Review Committee Member, IEEE Int’l Symposium on Circuits and Systems, 2005~2013
     Industrial Session Organizer, VLSI-DAT, 2013
     Technical Committee Member, IEEE TENCON, 2007/11
     Technical Committee Member, IEEE APCCAS, 2004/12
     Technical Committee Member, Intl. Analog VLSI Workshop, 1999
     Track Co-chair, IEEE Int’l Conference on Communications, Circuits and Systems, Track TDICAS, 2008/5
     Organizing Committee Chair, Int’l Electron Devices and Materials Symposia, 2008/11
     Technical Program Co-chair, The Int’l Symp. on Nanoelectronic Circuits and Giga-scale Systems, 2004/1
     Co-organizer, the Multimedia Systems Technology session for the IEEE ISCAS Tutorial Program, 1995
     Session Chair, IEEE Int’l Symposium on Circuits and Systems, 2009, 2004
     Session Chair, The 6th Int’l Conference on Information, Communications, and Signal Processing, 2007/12
     Session Chair, IEEE APCCAS, 2004
     Session Chair, IEEE Asia Pacific conf. on ASICs, 2004, 2000
    -Domestic:
     General Chair, The 22nd VLSI Design/CAD Symposium, 2011/8
     General Chair, The 13rd Workshop on Compiler Techniques for High Performance Computing, 2007/3
     General Chair, IP Qualification Workshop, 2006, 2005
     Technical Program Chair, The 14th VLSI Design/CAD Symposium, 2003/8
     Organizing Committee Member, 2007 Global Chinese Energy Material Forum, 2007/4
     Technical Committee Member, The 15th VLSI Design/CAD Symposium, 2004
     Tutorial Chair, The 18th VLSI Design/CAD Symposium, 2007
     Session Chair, The VLSI Design/CAD Symposium, 2001, 2000, 1998
    *Committee member
     National Chip Implementation Center, Taiwan, Advisory Committee Members, 2005~2010
     Taiwan Integrated Circuits Design Association, Member of Council, 2004~2008, 2010~present
     NSC Microelectronics division-VLSI/CAD group, Steering Committee Member, 1998, 1999, 2001
    *Panel reviewer for competitive proposals
     NSC Microelectronics division-VLSI/CAD group, 2009~2011
     SOC National Project, 2006~2008, 2010
     National Program on Intelligent Electronics, 2011~present
    *External reviewer
     National Science Council research proposals
     CIC chip submission proposals
     Ministry of Economic Affairs - SBIR project proposals
    *Technical reviewer for many IEEE Journal and conference papers
  11.  
  12. Awards
  13. Distinguished Lecturer by the IEEE Circuits and Systems Society for years 2013 and 2014
    Fellow of the Institution of Engineering and Technology, 2011
    Excellent Industry-University Cooperation Award, National Chung Hsing Univ., 2011
    Outstanding Teacher Award, Dept. of Electrical Engineering, National Chung Hsing Univ., 2000, 2001, 2002, 2004, 2010
    Excellent Industry-University Cooperation Award, College of Engineering, National Chung Hsing Univ., 2010
    Distinguished Teacher Evaluation Award, College of Engineering, National Chung Hsing Univ., 2009
    IEEE Senior Member, 2009
    Directed students to win a Design Completion Award in “Ministry of Education, IC Design Contest – Analog Circuits Design Category,”2009
    Directed students to win an Excellent Award in “The First Richtek Power IC Design and System Application Contest – Power IC Design Category,” 2009
    Outstanding Research Project Award, National Chung Hsing University,2006
    Distinguished Teaching Award, National Chung Hsing University, 2004
    Directed students to win an Excellent Award in “Ministry of Education, Embedded Software Design Contest – Integrated Application Category,”2005
    Directed a student to win an Excellent Chip Award in “CIC Chip Implementation Achievements – Analog Category,” 2005
    Directed a student to win an Outstanding Award in “Student Paper Contest –College of Engineering, NCHU,”2004
    Directed a student to win an Outstanding Award in “Ministry of Education, Silicon IP Design Contest – Soft IP Category,” 2001
    Listed in the Marquis Who’s Who in the World 2000
    National Science Council Research Award, Taiwan, 1997 and 1998
    Outstanding Academic Achievement Award, OISS, Univ. of Southern California, 1993 and 1995
    Tau Beta Pi Honorary Member, 1993
  14.  
  15. Selected Publications
    1. A.期刊論文
      1. 1.
      2. Robert C.-H. Chang, Chih-Hung Lin, Ming-Fan Wei, Kuang-Hao Lin, and Shiue-Ru Chen, “High-precision real-time premature ventricular contraction (PVC) detection system based on Wavelet transform,” Journal of Signal Processing Systems, accepted, June 2013. (SCI、EI)
      1. 2.
      2. Hou-Ming Chen, Robert C. Chang, and Kuang-Hao Lin, “A high-efficiency monolithic DC-DC PFM boost converter with parallel power MOS technique,” VLSI Design, April 2013. (EI)
      1. 3.
      2. Robert Chen-Hao Chang, Hung-Lieh Chen, Kuang-Hao Lin, Ming-Fan Wei, “Recursive QR decomposition architecture for MIMO-OFDM detection systems,” Journal of Circuits, Systems, and Computers, vol.22, no.2, pp.1250078-1-, March 2013. (SCI、EI)
      1. 4.
      2. Robert Chen-Hao Chang, Chih-Hung Lin, Kuang-Hao Lin, and Chien-Lin Huang, “, “Implementation of carrier frequency offset and IQ imbalance compensation in OFDM systems ,” International Journal of Electrical Engineering, vol.17, no.4, pp.251-259, August 2010. (EI)
      1. 5.
      2. Robert Chen-Hao Chang, Chih-Hung Lin, Kuang-Hao Lin, Chien-Lin Huang, and Feng-Chi Chen, “Iterative QR decomposition architecture using the modified Gram-Schmidt algorithm for MIMO systems,” IEEE Trans. on Circuits and Systems – I: Regular Paper, vol.57, no.5, pp.1095-1102, May 2010. (SCI、EI)
      1. 6.
      2. Robert C. Chang, Hou-Ming Chen, Wang-Cyuan Jheng, Chu-Hsiang Chia, Pui-Sun Lei and Zong-Yui Lin, “Adaptive Sense Current Control for DC-DC Boost Converters to Get Accurate Voltage,” IEICE Trans. on Electronics, vol.E92-C, no.8, August 2009. (SCI、EI)
      1. 7.
      2. Robert C. Chang, Hou-Ming Chen, Chu-Hsiang Chia, and Pui-Sun Lei, “An exact current-mode PFM boost converter with dynamic stored energy technique,” IEEE Trans. on Power Electronics, vol.24, no.4, pp.1129-1134, April 2009. (SCI、EI)
      1. 8.
      2. Robert C. Chang, Hou-Ming Chen and Po-Jen Huang, “A Multiphase-Output Delay-Locked Loop with a Novel Start-Controlled Phase/Frequency,” IEEE Transactions on Circuits and Systems I, vol.55, no.9, pp.2483-2490, October 2008. (SCI、EI)
      1. 9.
      2. Kuang-Hao Lin, Robert C. Chang, Hsin-Lei Lin, and Ching-Fen Wu, “Analysis and architecture design of a downlink M-modification MC-CDMA system using the Tomlinson-Harashima precoding technique,” IEEE Trans. on Vehicular Technology, vol.57, no.3, pp.1387-1397, May 2008. (SCI、EI)
      1. 10.
      2. Hsin-Lei Lin, Robert C. Chang, and Hung-Lien Chen, “A high speed SDM-MIMO decoder using efficient candidate searching for wireless communication,” IEEE Trans. on Circuits and Systems II, vol.55, no.3, pp.289-293, March 2008. (SCI、EI)
      1. 11.
      2. Robert C. Chang, Hsin-Lei Lin, and I-Hao Wang, “Low-power 8-bit SCSDL CLA with a novel split-level charge-sharing differential logic (SCSDL),” Journal of Circuits, Systems, and Computers, vol.16, no.3, pp.389-402, June 2007. (SCI、EI)
      1. 12.
      2. Hsin-Lei Lin, Robert C. Chang, Kuang-Hao Lin, Chia-Chen Hsu, “Implementation of synchronization for 2x2 MIMO WLAN system,” IEEE Trans. on Consumer Electronics, vol.52, no.3, pp.766-773, August 2006. (SCI、EI)
      1. 13.
      2. Robert C. Chang, Po-Chung Hung and Hsin-Lei Li, “Low Power Energy Recovery Complementary Pass-Transistor Logic,” Journal of Circuits, Systems, and Computers, vol.15, no.4, pp.491-504, August 2006. (SCI、EI)
      1. 14.
      2. Robert C. Chang, Lung-Chih Kuo, and Hou-Ming Chen, “A Low-Voltage Low-Power CMOS Phase-Locked Loop,” Journal of Circuits, Systems, and Computers, vol.14, no.5, pp.997-1006, October 2005. (SCI、EI)
      1. 15.
      2. R. C. Chang and B.-H. Lim,, “Efficient IP Routing Table VLSI Design for Multigigabit Routers,” IEEE Trans. on Circuits and Systems, Part I, vol.51, no.4, pp.700-708, April 2004. (SCI、EI)
      1. 16.
      2. H. Lin, J. Lin, R. C. Chang, “Inversion Layer Induced Body Current in SOI MOSFETs with Body Contacts,” IEEE Electron Device Letters, vol.24, no.2, pp.111-113, February 2003. (SCI、EI)
      1. 17.
      2. R. C. Chang, P.-C. Hung, I.-H. Wang, “Complementary pass-transistor energy recovery logic for low power applications,” IEE Proceedings on Computers and Digital Techniques, vol.149, no.4, pp.146-151, July 2002. (SCI、EI)
      1. 18.
      2. R. C. Chang and B.-H. Lim, “Efficient IP Routing Table Lookup Scheme,” IEE Proceedings on Communications, vol.149, no.2, pp.77-82, April 2002. (SCI、EI)
      1. 19.
      2. R. C. Chang, L.-C. Hsu, M.-C. Sun, “A low-power and high-speed D flip-flop using a single latch,” Journal of Circuits, Systems, and Computers, vol.11, no.1, pp.51-55, February 2002. (SCI、EI)
      1. 20.
      2. R. C. Chang, M.-C. Li, “Implementation of folding and interpolating analog-to-digital converter,” Journal of Engineering, NCHU, vol.12, no.3, pp.157-166, November 2001.
      1. 21.
      2. R. C. Chang, B.-H. Lim, C.-Y. Hsieh, “VLSI implementation of an ATM switch controller with multicast functions,” Journal of the Chinese Institute of Engineers, vol.24, no.1, pp.9-18, January 2001. (SCI、EI)
      1. 22.
      2. R. C. Chang, D.-S. Cho, “Design and implementation of a low-power subranging analog-to-digital converter,” Journal of Engineering, NCHU, vol.11, no.1, pp.25-35, March 2000.
      1. 23.
      2. R. C. Chang, C.-Y. Hsieh, “Design of multicast ATM switch,” IEE Electronics Letters, vol.34, no.22, pp.2090-2091, October 1998. (SCI、EI)
      1. 24.
      2. E. Y. Chou, B. J. Sheu, R. C. Chang, “VLSI design of optimization and image processing cellular neural networks,” IEEE Trans. on Circuits and Systems, Part I, vol.44, no.1, pp.12-20, January 1997. (SCI、EI)
      1. 25.
      2. R. C. Chang, B. J. Sheu, J. Choi, D. C. Chen, “Programmable-weight building blocks for analog VLSI neural network processors,” Journal of Analog Integrated Circuits and Signal Processing, vol.9, no.3, pp.215-230, April 1996. (SCI、EI)
      1. 26.
      2. S. H. Bang, J. Choi, B. J. Sheu, R. C. Chang, “A compact low-power VLSI transceiver for wireless communication,” IEEE Trans. on Circuits and Systems, Part I, vol.42, no.11, pp. 933-945, November 1995. (SCI、EI)
      1. 27.
      2. S. M. Gowda, B. J. Sheu, R. C. Chang, “Effective parameter extraction using multiple-objective function for VLSI circuits,” Journal of Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers: Boston, MA, vol.5, no.2, pp.121-133, March 1994. (SCI、EI)
      1. 28.
      2. L.-S. Lee, C.-Y. Tseng, H.-Y. Gu, F.-H. Liu, C.-H. Chang, et al., “Golden Mandarin (I) - A real-time Mandarin speech dictation machine for Chinese language with very large vocabulary,” IEEE Trans. on Speech and Audio Processing, vol.1, no.2, pp.158-179, April 1993. (SCI、EI)
      1. 29.
      2. L.-S. Lee, C.-Y. Tseng, Y. H. Lin, Y. Lee, S.-L. Tu, H.-Y. Gu, F.-H. Liu, C.-H. Chang, S.-H. Hsieh, C.-H. Chen, K.-R. Huang, “System Description of Golden Mandarin (I) Voice Input System for Unlimited Chinese Characters,” Computer Processing of Chinese and Oriental Languages, vol.5, no.4, pp.314-329, November 1991.
      1. 30.
      2. L.-S. Lee, C.-Y. Tseng, F.-H. Liu, C.-H. Chang, H.-Y. Gu, S.-H. Hsieh, C.-H. Chen, “Special speech recognition approaches for the highly confusing Mandarin syllables based on hidden Markov models,” Computer Speech and Language, vol.5, pp.181-201, May 1991. (SCI、EI)
    2. B.研討會論文
      1. 1.
      2. Chih-Hung Lin, Robert Chen-Hao Chang, Tz-Han Pang, and Kuang-Hao Lin, “A low-complexity bio-medical signal receiver for wireless body area network,” International SoC Design Conference (ISOCC), Jeju, Korea, November 2012.
      1. 2.
      2. Chu-Hsiang Chia, Pui-Sun Lei, Robert Chen-Hao Chang, “A High speed converter with efficiency improvement circuit and transient detector,” IEEE Intl. Symp. on Circuits and Systems, Seoul, Korea, May 2012. (EI)
      1. 3.
      2. Chu-Hsiang Chia, Pui-Sun Lei, Robert Chen-Hao Chang, and Yu-Bin Hong, “A fully integrated DC-DC converter for dynamic voltage scaling applications,” IEEE Intl. Symp. on Circuits and Systems, Seoul, Korea, May 2012. (EI)
      1. 4.
      2. Chu-Hsiang Chia, Pui-Sun Lei, Robert Chen-Hao Chang, and Pei-Wei Ko, “A Multi-channel LED driver with accurate current control and adjustable LED numbers,” 8th International Caribbean Conference on Devices, Circuits and Systems, Playa del Carmen, Mexico, March 2012.
      1. 5.
      2. Kuang-Hao Lin, Yu-Ya Gao, and Robert Chen-Hao Chang, “A high-throughput modified merge sorting for MIMO detection systems,” The 22th VLSI Design/CAD Symposium, Yunlin, Taiwan, August 2011.
      1. 6.
      2. Pui-Sun Lei, Chu-Hsiang Chia, Robert Chen-Hao Chang, and Yi-Mei Liu, “Design of a low-voltage high-efficiency power management circuit for the solar-cell system,” The 22th VLSI Design/CAD Symposium, Yunlin, Taiwan, August 2011.
      1. 7.
      2. Chu-Hsiang Chia, Pui-Sun Lei, and Robert Chen-Hao Chang, “A high-efficiency PWM DC-DC buck converter with a novel DCM control under light-load,” IEEE Intl. Symp. on Circuits and Systems, Rio, Brasil, May 2011. (EI)
      1. 8.
      2. Chih-Hung Lin, Robert Chen-Hao Chang, Kuang-Hao Lin, and Yang-Yu Lin, “Implementation of channel estimation for MIMO-OFDM systems,” International SoC Design Conference (ISOCC), Incheon, Korea, November 2010.
      1. 9.
      2. Chih-Hung Lin, Alex Chien-Lin Huang, Robert Chen-Hao Chang, and Kuang-Hao Lin, “Low-power design of variable block-size LDPC decoder using nanometer technology,” IEEE Intl. Symp. on Circuits and Systems, Paris, France, May 2010. (EI)
      1. 10.
      2. Kuang-Hao Lin, Chih-Hung Lin, Robert Chen-Hao Chang, I-Ju Chang, “Reconfigurable K-Best algorithm for MIMO detection systems,” 7th International Conference on Information, Communications and Signal Processing, Macau, December 2009. (EI)
      1. 11.
      2. Chih-Hung Lin, Kuang-Hao Lin, Robert Chen-Hao Chang, and Chien-Lin Huang, “Implementation of carrier frequency offset and IQ imbalance compensation in OFDM systems,” National Symposium on Telecommunications, Kaohsiung, Taiwan, December 2009.
      1. 12.
      2. Kuang-Hao Lin, Chih-Hung Lin, Robert Chen-Hao Chang, and Feng-Chi Chen, “Iterative QR decomposition architecture using the modified Gram-Schmidt algorithm,” IEEE Intl. Symp. on Circuits and Systems, Taipei, Taiwan, May 2009. (EI)
      1. 13.
      2. Kuang-Hao Lin, Robert C. Chang, I-Ju Chang, Chih-Hung Lin, and Chien-Lin Huang, “An improved K-best detector for MIMO WLAN systems,” The 19th VLSI Design/CAD Symposium, Kenting, Taiwan, August 2008.
      1. 14.
      2. Kuang-Hao Lin, Robert C. Chang, Chien-Lin Huang, Feng-Chi Chen, and Shih-Chun Lin, “Implementation of QR decomposition for MIMO-OFDM detection systems,” The 15th IEEE Int. Conf. on Electronics, Circuits and Systems, Malta, pp.57-60, August 2008.
      1. 15.
      2. Hou-Ming Chen, Robert C. Chang, Pui-Sun Lei, “An exact, high-efficiency PFM DC-DC boost converter with dynamic stored energy,” The 15th IEEE Int. Conf. on Electronics, Circuits and Systems, Malta, pp.622-625, August 2008.
      1. 16.
      2. Kuang-Hao Lin, Robert C. Chang, Chien-Lin Huang, and Sheng-Dong Wu, “Construction of the cyclic block-type LDPC codes for low complexity hardware implementation,” The 15th IEEE Int. Conf. on Electronics, Circuits and Systems, Malta, pp.1187-1190, January 2008.
      1. 17.
      2. Hou-Ming Chen, Robert C. Chang, Jian-Lin Wu, “A low-voltage integrated current-mode boost converter for portable power supply,” The 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco, December 2007.
      1. 18.
      2. Kuang-Hao Lin, Robert C. Chang, and Sheng-Dong Wu, “Architecture of the modified block-type low-density parity-check code decoding design,” The 6th International Conference on Information, Communications, and Signal Processing, Singapore, December 2007.
      1. 19.
      2. Hou-Ming Chen, Robert C. Chang, and Chih-Liang Huang, “Low-voltage zero quiescent current PFM boost converter for portable devices,” IEEE International SOC Conference, Hsinchu, Taiwan, September 2007.
      1. 20.
      2. Nan-Xiong Hung, Wei-Shan Jiang, Bo-Cang Wu, Ming-Yuan Tsao, Han-Wen Liu1, Chen-Hao Chang, Miin-Shyue Shiau, Hong-Chong Wu, Ching-Hwa Cheng, and Don-Gey Liu, “A low power source driver of small chip area for QVGA TFT-LCD applications,” The 7th International Meeting on Information Display, Daegu Korea, August 2007.
      1. 21.
      2. Hsin-Lei Lin, Hung-Lien Chen, Robert C. Chang, “JQRPSD detection with low complexity for SDM MIMO wireless communication system,” International Symposium on VLSI Design, Automation, and Test, Hsinchu, Taiwan, April 2007.
      1. 22.
      2. Wei-Shan jiang, Han-Wen Liu, Nan-Xiong Hung, Ming-Yuan Tsao, Robert C. Chang, Don-Gey Liu, “One quiescent current and chip area efficient architecture of TFT-LCD source driver for portable applications,” Proceedings of Asia Display 2007, Shanghai, China, pp.1-39-43, March 2007.
      1. 23.
      2. Kuang-Hao Lin, Hsin-Lei Lin, Robert C. Chang, Ching-Fen Wu, “Hardware architecture of improved Tomlinson-Harashima precoding for downlink MC-CDMA,” 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, December 2006. (EI)
      1. 24.
      2. Hou-Ming Chen, Ding-Da Jiang and Robert C. Chang, “Monolithic boost converter with an adaptable current-limited PFM scheme,” 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, December 2006. (EI)
      1. 25.
      2. Wei-Shan Jiang, Ming-Yuan Tsao, Nan-Xiong Hung, Don-Gey Liu, Robert Chen-Hao Chang, Han-Wen Liu, “One novel 262K-colors source driver architecture of TFT-LCD used in portable applications,” The 17th VLSI Design/CAD Symposium, Hua-Lein, Taiwan, August 2006.
      1. 26.
      2. Wei-Shan Jiang, Ming-Yuan Tsao, Nan-Xiong Hung, Don-Gey Liu, Chen-Hao Chang, Han-Wen Liu, “An area efficient source driver for 262K-colors TFT-LCD be used in mobile phone application,” 2006 Taiwan Display Conference, G007, Taipei, Taiwan, June 2006.
      1. 27.
      2. H.-L. Lin, H. Lin, R. C. Chang, S.-W. Chen, C.-Y. Liao, C.-H. Wu, “A high-speed highly pipelined 2n-point FFT architecture for a dual OFDM processor,” Mixed Design 2006, Gdynia, Poland, pp.627-631, June 2006.
      1. 28.
      2. Hou-Ming Chen, Chih-Liang Huang, Robert C. Chang, “A new temperature-compensated CMOS bandgap reference circuit for portable applications,” IEEE Intl. Symp. on Circuits and Systems, Kos, Greece, May 2006. (EI)
      1. 29.
      2. Kuang-Hao Lin, Hsin-Lei Lin, Shih-Ming Wang, Robert C. Chang, “Implementation of digital IQ imbalance compensation in OFDM WLAN receivers,” IEEE Intl. Symp. on Circuits and Systems, Kos, Greece, May 2006. (EI)
      1. 30.
      2. Hsin-Lei Lin, Chia-Chen Hsu, Robert C. Chang, “Implementation of synchronization for 2x2 MIMO WLAN systems,” International Conference on Consumer Electronics, Las Vegas, USA, January 2006.
      1. 31.
      2. Cheng-Hui Chang, Hou-Ming Chen, and Robert C. Chang, “A 2.3V CMOS monolithic, 84% efficiency PFM control DC-DC boost converter for white LEDs driver IC,” The Sixth International Conference on Power Electronics and Drive Systems, Kuala Lumpur, Malaysia, November 2005.
      1. 32.
      2. Larry Li, J. Hou-Ming Chen, Robert C. Chang, “A low jitter delay-locked loop with a realignment duty cycle corrector,” IEEE Int’l SOC Conference, Washington DC, pp.75-76, September 2005.
      1. 33.
      2. Hou-Ming Chen and Robert C. Chang, “Low power and area effective curvature-compensated CMOS bandgap reference,” The 16th VLSI Design/CAD Symposium, Hua-Lein, Taiwan, August 2005.
      1. 34.
      2. Hsin-Lei Lin, Chia-Chen Hsu, Robert C. Chang, Ching-Fen Wu, “Implementation of synchronization for dual-band wireless LAN systems,” The 16th VLSI Design/CAD Symposium, Hua-Lein, Taiwan, August 2005.
      1. 35.
      2. Cheng-Hui Chang and Robert C. Chang, “A Novel Current Sensing Circuit for a Current-Mode Control CMOS DC-DC Buck Converter,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test, Hsinchu, Taiwan, pp.120-123, April 2005. (EI)
      1. 36.
      2. Hsin-Lei Lin, Robert C. Chang, Ming-Tsai Chan, “Design of a novel radix-4 Booth multiplier,” IEEE Asia-Pacific Conference on Circuits and Systems, Tainan, Taiwan, pp.837-840, December 2004. (EI)
      1. 37.
      2. Hsin-Lei Lin, Hongchin Lin, Yu-Chuan Chen and Robert C. Chang, “A novel pipelined fast fourier transform architecture for double rate OFDM systems,” IEEE Workshop on Signal Processing Systems (SiPS), Austin, Texas, USA, pp.7-11, October 2004. (EI)
      1. 38.
      2. P.-J. Huang, H.-M. Chen, R. C. Chang, “A novel start-controlled phase/ frequency detector for multiphase-output delay-locked loops,” The Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Fukuoka, Japan, pp.68-71, August 2004.
      1. 39.
      2. Y.-Y. Sung, R. C. Chang, “A novel CMOS double-edge triggered flip-flop for low-power applications,” IEEE Intl. Symp. on Circuits and Systems, Vancouver, Canada, pp.II-665-668, May 2004. (EI)
      1. 40.
      2. C.-S. Chen, R. C. Chang, “A new prescaler for fully integrated 5-GHz CMOS frequency synthesizer,” IEEE Intl. Symp. on Circuits and Systems, Vancouver, Canada, pp.IV-245-248, May 2004. (EI)
      1. 41.
      2. Y.-Y. Sung, R. Chang, “An ultra low-power double-edge triggered flip-flop,” The 14th VLSI Design/CAD Symposium, Hua-Lein, Taiwan, pp.109-112, August 2003.
      1. 42.
      2. H.-L. Lin, R. C. Chang, Chih-Hao Huang, H. Lin, “A flexible design of a decision feedback equalizer and a novel CCK technique for wireless LAN systems,” IEEE Intl. Symp. on Circuits and Systems, Bangkok, Thailand, May 2003. (EI)
      1. 43.
      2. H.-L. Lin, R. C. Chang, “Design of a decision feedback equalizer for WLAN systems,” The 13th VLSI Design/CAD Symp., Taidong, Taiwan, pp.67-70, August 2002.
      1. 44.
      2. R. C. Chang, B.-H. Lim, “Efficient IP routing table VLSI design for multigigabit routers,” IEEE Intl. Symp. on Circuits and Systems, Phoenix, AZ, pp.TA2.05.04, May 2002. (EI)
      1. 45.
      2. R. C. Chang, P.-C. Hung, “Low power energy recovery complementary pass-transistor logic,” The 12th VLSI Design/CAD Symp., Hsinchu, Taiwan, pp.B2.13.1-4, August 2001.
      1. 46.
      2. R. C. Chang, M.-C. Li, “Implementation of folding and interpolating analog-to-digital converter,” The 12th VLSI Design/CAD Symp., Hsinchu, Taiwan, pp.B1.1.1-4, August 2001.
      1. 47.
      2. R. C. Chang, B.-H. Lim, “Hardware design of an IP routing lookup table,” The 12th VLSI Design/CAD Symp., Hsinchu, Taiwan, pp.C2.12.1-4, August 2001.
      1. 48.
      2. R. C. Chang, L.-C. Kuo, “A differential-type CMOS phase frequency detector,” The second IEEE Asia Pacific conference on ASICs, Cheju, Korea, pp.61-64, August 2000.
      1. 49.
      2. R. C. Chang, C.-T. Huang, “A 1.5V, 10-bit, 50-MS/s CMOS pipelined ADC using current-mode signals,” The 11th VLSI Design/CAD Symp., Kenting, Taiwan, pp.361-364, August 2000.
      1. 50.
      2. R. C. Chang, L.-C. Kuo, “A 1.5V 900MHz CMOS phase-locked loop,” The 11th VLSI Design/CAD Symp., Kenting, Taiwan, pp.285-288, August 2000.
      1. 51.
      2. R. C. Chang, L.-C. Kuo, “A new low-voltage charge pump circuit for PLL,” IEEE Intl. Symp. on Circuits and Systems, Geneva, Switzerland, pp.V-701-704, August 2000. (EI)
      1. 52.
      2. R. C. Chang, L.-C. Hsu, M.-C. Sun, “Design of a new low-power high-speed D flip-flop,” The 10th VLSI Design/CAD Symp., Nantou, Taiwan, pp.225-228, August 1999.
      1. 53.
      2. R. C. Chang, L.-C. Kuo, C.-Y. Hsieh, “VLSI implementation of a multicast ATM switch controller,” IEEE Intl. Symp. on Circuits and Systems, Orlando, FL, pp.I129-I132, May 1999. (EI)
      1. 54.
      2. R. C. Chang, C.-T. Huang, “A 10-bit fast pipelined ADC using current-mode techniques,” 1999 Intl. Analog VLSI Workshop, Taipei, Taiwan, pp.3-6, May 1999.
      1. 55.
      2. H. Lin, R. C. Chang, S.-C. Tsai, “Radix-8 divider algorithm and implementation,” The 9th VLSI Design/CAD Symp., pp.243-246, August 1998.
      1. 56.
      2. R. C. Chang, C. -Y. Hsieh, “VLSI design of an ATM switch controller,” The 9th VLSI Design/CAD Symp., pp.251-254, August 1998.
      1. 57.
      2. K.-L. Huang, R. C. Chang, T.-S. Chiu, “An 8-bit 20MHz CMOS A/D converter,” The 9th VLSI Design/CAD Symp., pp.107-110, August 1998.
      1. 58.
      2. R. C. Chang, C.-Y. Hsieh, “A new memory controller for the shared multibuffer ATM switch with multicast functions,” IEEE Intl. Symp. on Circuits and Systems, Monterey, CA, May 1998. (EI)
      1. 59.
      2. C.-Y. Hsieh, R. C. Chang, “A novel ATM switch architecture with multicast functions for multimedia applications,” Intl. Symp. on Multimedia Information Processing, Taipei, Taiwan, pp.430-434, December 1997.
      1. 60.
      2. C.-Y. Hsieh, R. C. Chang, “A new shared multibuffer ATM switch architecture with cyclic address queue for multicast functions,” The Third Symp. on Computer & Communication Technology, Chungli, Taiwan, pp.156-159, October 1997.
      1. 61.
      2. R. R.-B. Sheen, O. T.-C. Chen, R. C. Chang, “A 1.3V 1.04GHz - 1.30GHz CMOS phase-locked loop,” IEEE 40th Midwest Symp. on Circuits and Systems, Sacramento, CA, August 1997. (EI)
      1. 62.
      2. E. Y. Chou, B. J. Sheu, T. H. Wu, R. C. Chang, “VLSI design of densely-connected array processors,” IEEE Intl. Conf. on Computer Design, Austin, TX, pp.492-497, October 1995. (EI)
      1. 63.
      2. R. C. Chang, B. J. Sheu, S. H. Bang, “Current-mode implementation of CNNs with annealing capability,” World Congress on Neural Networks, Washington, DC, pp.II-488-491, July 1995. (EI)
      1. 64.
      2. B. J. Sheu, S. H. Bang, R. C. Chang, “A cellular neural network with optimized performance for wireless communication receivers,” World Congress on Neural Networks, Washington, DC, pp.II-660-664, July 1995. (EI)
      1. 65.
      2. B. J. Sheu, R. C. Chang, T. H. Wu, S. H. Bang, “VLSI-compatible cellular neural networks with optimal solution capability for optimization,” IEEE Intl. Symp. on Circuits and Systems, Seattle,WA, pp.1165-1168, April 1995. (EI)
      1. 66.
      2. S. H. Bang, B. J. Sheu, R. C. Chang, “Maximum likelihood sequence estimation of communication signals by a Hopfield neural network,” IEEE Intl. Conf. on Neural Networks, Orlando, FL, pp.3369-3374, June 1994. (EI)
      1. 67.
      2. R. C. Chang, B. J. Sheu, “An analog MOS model for circuit simulation and benchmark test results,” IEEE Intl. Symp. on Circuits and Systems, London, England, pp.309-312, May 1994. (EI)
      1. 68.
      2. B. J. Sheu, R. C. Chang, T. H. Wu, “Neural information processing in analog current-mode VLSI,” Intl. Symp. on Artificial Neural Networks, Hsinchu, Taiwan, R.O.C., pp.B-01-10, December 1993. (EI)
      1. 69.
      2. R. C. Chang, B. J. Sheu, S. M. Gowda, “Reliability assessment of self-timed VLSI circuits,” IEEE Custom Integrated Circuits Conference, San Diego, CA, pp.30.3.1-4, May 1993. (EI)
      1. 70.
      2. S. M. Gowda, B. J. Sheu, R. C. Chang, “Advanced VLSI circuit simulation using the BSIM_plus model,” IEEE Custom Integrated Circuits Conference, San Diego, CA, pp.14.3.1-5, May 1993. (EI)
      1. 71.
      2. L.-S. Lee, C.-Y. Tseng, F.-H. Liu, C.-H. Chang, H.-Y. Gu, S.-H. Hsieh, C.-H. Chen, “Special Speech Recognition Approaches for the Highly Confusing Mandarin Syllables Based on Hidden Markov Models,” The First ROC-Japan Seminar on New Speech Recognition Methods, Hsinchu, Taiwan, pp.1-21, November 1991.
      1. 72.
      2. L.-S. Lee, C.-Y. Tseng, Y. H. Lin, Y. Lee, S.-L. Tu, H.-Y. Gu, F- H. Liu, C.-H. Chang, S.-H. Hsieh, C.-H. Chen, K.-R. Huang, “System Description of the Golden Mandarin (I) Voice Input System for Unlimited Chinese Characters,” International Conference on Computer Processing of Chinese and Oriental Languages, CLCS, Taipei, Taiwan, pp.45-50, August 1991.
      1. 73.
      2. L.-S. Lee, C.-Y. Tseng, Y. H. Lin, Y. Lee, S. L. Tu, H.-Y. Gu, F.-H. Liu, C.-H. Chang, S.-H. Hsieh, C.-H. Chen, K.-R. Huang, “A fully parallel Mandarin speech recognition system with very large vocabulary and almost unlimited texts,” IEEE Intl. Symp. on Circuits and Systems, Singapore, pp.I-578-581, June 1991. (EI)
      1. 74.
      2. L.-S. Lee, C.-Y. Tseng, F.-H. Liu, H.-Y. Gu, C.-H. Chang, S.-H. Hsieh, C.-H. Chen, “A real-time Mandarin dictation machine for Chinese language with unlimited texts and very large vocabulary,” IEEE Intl. Conf. on Acoustics, Speech, and Signal Processing, Albuquerque, NM, pp.65-68, April 1990. (EI)
      1. 75.
      2. C.-H. Chang, L.-S. Lee, “Training and simulation for syllable models in a Mandarin dictation machine,” Proceedings of National Computer Symp., Taipei, Taiwan, R.O.C., pp.738-746.
    3. C.專書
      1. 1.
      2. 張振豪、林泓均、陳後守、鄧洪聲、江雨龍、蘇武昌等作;林俊良主編, “3C科技與生活,” 冠唐國際圖書, July 2010.
      1. 2.
      2. R. C. Chang, B. J. Sheu, “Transmission Gates for High-Speed Computing,” The Circuits and Filters Handbook, Prof. Wai-Kai Chen, editor-in-chief, CRC Press, pp. 1903-1921, May 1995; also in 2nd edition, pp.1829–1846.
      1. 3.
      2. B. J. Sheu, R. C. Chang, “VLSI Cellular Neural Networks for Optimization,” Microsystems Technology for Multimedia Spplications, B. Sheu, M. Ismail, E. Sanchez-Sinencio, T. H. Wu, eds., IEEE Press, pp.477-490, April 1995.
    4. D.技術報告
      1. 1.
      2. Chen-Hao Chang, “網路處理晶片設計,” 工程科技通訊月刊第74期 (Engineering Science & Technology Bulletin, NSC 74), pp.168-172, June 2004.
      1. 2.
      2. R. C. Chang, “Introduction to several IP routing lookup scheme,” IC Design Magazine, vol. 16, July 2001.
      1. 3.
      2. R. C. Chang, “Introduction to Low-power IC Design,” Electronic Monthly, no. 70, May 2001.
      1. 4.
      2. B. J. Sheu, R. C. Chang, T. H. Wu, “Applications, design, and test of mixed-signal ICs,” Modern Engineering and Technology Seminar, Electronics Session, Taipei, Taiwan, December 1994.
      1. 5.
      2. R. C. Chang, B. J. Sheu, “JPEG/MPEG systems: software implementation and hardware design,” Proc. of the Signal and Image Processing Institute Annual Research Review, Marina del Rey, CA, February 1993.
    5. E.專利
      1. 1.
      2. 林泓均、陳囿全、林心蕾、張振豪, “可處理雙輸入信號的管線式傅利葉轉換系統,” 中華民國發明專利,第I254215號,專利期間:2006年5月1日~2009年4月30日, .
      1. 2.
      2. 張振豪、黃聖紘、陳厚銘, “緩衝放大器及其自動歸零裝置,” 中華民國發明專利,第I294211號,專利期間:2008年3月1日~2025年3月24日, .
      1. 3.
      2. 張振豪、陳厚銘, “高速低功率零穩態電流之啟動電路,” 中華民國發明專利,第I307215號,專利期間:2009年3月1日~2025年8月14日, .
      1. 4.
      2. 張振豪、陳厚銘, “程式化直流轉直流升壓轉換電路,” 中華民國發明專利,第I355791號,專利期間:2012年1月1日~2028年3月31日, .
      1. 5.
      2. 張振豪、賈竹翔, “直流轉直流脈衝寬度調變轉換電路,” 中華民國發明專利,第I389434號,專利期間:2013年3月11日~2029年2月16日, .
      1. 6.
      2. 張振豪、林光浩、張宜濡, “多輸入多輸出偵測系統之 K-Best 球型解碼器及其方法 ,” 中華民國發明專利,第I392295號,專利期間:2013年4月1日~2028年10月6日, .
 
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